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Online Resumes with "Standard cells"
USC NCG EE ASIC CAD Digital Circuit Analog Mixed Signal Verilog Hardware
April 1, 2009 To whom this may concern: I graduated from University of Southern California on May 15, 2009. I am currently looking for full-time, co-op, or internship related to ASIC design, Mixed-Signal Circuit, and CAD. I believe ASIC Engineer best suits my background. In Taiwan, I was a Cell Library engineer responsible for building Powerchip Semiconductor 0.15μm/0.18μm standard cell/IO library. In order to ensure t...
Tags for this Online Resume: USC, NCG, EE, ASIC, CAD, Digital, Circuit, Analog, Mixed Signal, Verilog, Hardware, cadence, synopsys, Hspice, mentor, magma
Sr mask designer - analog/RF/digital
contract mask design doing analog /RF or digital layouts
Ideal Companies: qualcomm, intel, freescale
Tags for this Online Resume: analog, RFIC, layout, designer, Cadence, Checkmate, dls, genesis
RESUME
Satish Chakkirala 1746 Ximeno Avenue, Apt # 5 Long Beach, CA - 90815 (714)-7944564 satish.0722@gmail.com OBJECTIVE An internship/full time position in the field of Electronics Engineering. Quest to work in a real professional environment, where I can enhance my skills and widen spectrum of knowledge. Also to make an indelible mark in the organization that i serve. Education •California State University Long beach...
mask layout designer
Larry High 2217 W. Catalina Ave Mesa, Arizona, 85202 H (480) 969-3117 C (480) 229-8148 Email: high90@cox.net OBJECTIVE My objective is to contribute and grow in a competitive environment with highly motivated and talented people. I have over 28 years of experience in the field of Layout Design. I have worked with Analog, Digital and RF. I have also worked ...
Tags for this Online Resume: layout designer, mask designer
Physical design /Hardware engineer/ Structural Design Engineer
work for the company to contribute my hard work and bring my valid ideas to improve the company profiles.
Tags for this Online Resume: Verilog, IP, memories, Standard cells, Physical Design
Sr. Mask Designer
I have experience in Analog, Bipolar and CMOS Digital design. I am fluent with Cadence VXL, Calibre LVS, Calibre DRC and Hercules DRC and LVS. Experienced with the Pulsic Router for digital standard cell routing.
Tags for this Online Resume: Mask Layout, Mask Design, Layout Design, Photomask Layout, Phjotomask Design
Senior Research Technician - 5 Years of Experience - Near 02155
Qualifications * Basic and advanced training in operating FACS-BD-Aria- Analyzing Cell cycle and synchronization, Color sorting * Efficient at handling various cell lines-Setup & standardized the cell culture, maintained them for various cell based assay experiments. * Proficient at Performing fluorescence& Phase contrast imaging-Well acquainted with imaging software's * C14 certified for working and supervising non-product...
Tags for this Online Resume: Biomedical Industry, Cancer, Communication Skills, ELISA, FACS,
Chief Executive Officer - 20 Years of Experience - Near 78732
Summary of Experience and Skills I/O's chip floor planning in Burlington, Vermont and Essonne, France responsible for design and development of HDD arm electronics and controllers, communication products (Token Ring on a chip), VGA and XGA graphics control chips, RAMDACs, tape drive controllers, and fiber optic transceivers. * Developed and delivered IBM's first 'correct by construction' mixed Analog and Digital standard ce...
Tags for this Online Resume: Forecasting, Pricing, Imaging, MicroElectronics, P&L, Product Development, CMOS, Management, Networking, Cadence, sales, management, Sales management, Operations, Contract negotiation, Analog Design, microprocessor design, executive management, partnerships, ecosystem development, strategy
Electronic Drafter - 20 Years of Experience - Near 85224
CAREER SUMMARY * Master of integrated circuit layout design Extensive expertise and experience in layout floor planning, standard cell planning, hierarchical layout assembly, device matching, place and route of large digital and analog blocks, pad-ring, ESD clamps adjustment, post layout parasitic extraction and re-run timing/ power simulation, shielding and guard ringing, DFM, tape out GDSII format and E-beam mask generati...
Tags for this Online Resume: Layout, Cadence, Rf, Management, Wireless, Phase Lock Loop (PLL), PLL, Analog Circuit Design, Business Development, Circuit Design
Electrical Engineer - 17 Years of Experience - Near 84096
EXPERIENCE SUMMARY: * Overall experience of over 17 years in ASIC Design * Physical layout of standard cell blocks * Test development for silicon on Agilent 93K tester. * Chip route engineer for multiple ASIC designs * Custom layout of digital logic for DDR3 interface. * Memory BIST insertions and verification * Chip level floorplan implementation for multiple ASIC designs * Technical Lead for multiple ASIC designs
Tags for this Online Resume: Asic, ASIC Design, Cadence, Compiler, EDI, Electronic Data Interchange, Layout, Perl Programming Language, Physical Layouts
Computer Hardware Engineer - 20 Years of Experience - Near 94087
Tags for this Online Resume: Dsp, DSPs, Macro (Predefined Code), Decoder, Ethernet, Tape-out, Asic, Logic Design, Microprocessors, FPGA
