EXPERIENCE SUMMARY: * Overall experience of over 17 years in ASIC Design * Physical layout of standard cell blocks * Test development for silicon on Agilent 93K tester. * Chip route engineer for multiple ASIC designs * Custom layout of digital logic for DDR3 interface. * Memory BIST insertions and verification * Chip level floorplan implementation for multiple ASIC designs * Technical Lead for multiple ASIC designs

Highlights:

• Asic
• ASIC Design
• Cadence
• Compiler
• EDI
• Electronic Data Interchange
• Layout
• Perl Programming Language
• Physical Layouts