mask layout designer

Larry High 2217 W. Catalina Ave Mesa, Arizona, 85202 H (480) 969-3117 C (480) 229-8148 Email: high90@cox.net OBJECTIVE My objective is to contribute and grow in a competitive environment with highly motivated and talented people. I have over 28 years of experience in the field of Layout Design. I have worked with Analog, Digital and RF. I have also worked with many different types of processes including TSMC, AMS and Sub Micron. EDUCATION Grand Canyon University International Baptist College Mesa Community College (AA degree) Western Design Center (Graduate Certificate) Microchip in house classes (totaling 27) examples: cycle time focus, building trust, performance planning/measuring/monitoring, developing employees and team development. EMPLOYERS Texas Instruments, Dallas, TX Feb 2010 to Nov 2010 Contracted under Debbie Graf Universal CADworks (972) 423-1900 - Worked with submicron .65 nm processes, Cadence XL, multiple voltages, seven layer metals, memory parts and Hercules verification tools. Microchip Technology Inc, Chandler, AZ Aug 1995 to Aug. 2008 Layout Supervisor for Memory Jun 2006 to Aug 2008 - Worked with TSMC and in house processes with Cadence XL. Worked with Memory parts and Hercules verification tools. Documented all layout procedures. I have and extensive amount of experience working with Digital, Analog and Mixed Signal. I also have experience with RF. - Managed layout group in Chandler, AZ and off USA sights in India. Developed standard cell libraries and pad libraries. Individual block and top level layout planning and hook up. EEproms, flash, drams, srams, charge pumps, roms and controllers. I also worked on all areas of memory chips. - As a supervisor I spent approx 70% of my time doing layout and 30% of the time doing management. Layout Supervisor for Microcontroller Division Jan 2004 to Jun 2006 - Worked with TSMC and in house processes with Cadence XL. Used Hercules verification tools. Documented all layout procedures. Layout Supervisor for Analog Division Aug 1995 to Jan 2004 - Worked with TSMC and in house processes with Cadence XL. Used Hercules verification tools. Documented all layout procedures. Individual block and top level layout planning and hook up. Motorola Paging Division, Tempe, AZ Aug 1984 to Aug. 1995 - Worked with in house processes on microprocessors with LTL system. Western Design Center, Mesa, AZ July 1979 to Sept 1984 - Worked on microprocessor on Calma System. REFERENCES Brad Gunter Qualcomm in AZ (Design Engineer) (480)496-6223 Walt Holt Texas Instruments (Layout Designer) (214)886-0096 Bill Reno Microchip (Layout Designer) (602)809-1215 Kathy Mench Qualcomm (Layout Designer) Kathryn_mensch@yahoo.com Kerry Hogan Microchip (Layout Designer) (480)205-5850 Mike Chavez Maxim (Layout Design Manager) (480)203-5204 Bernie Chavez Maxim (Layout Design Manager) (480)220-0328 Rick Bellah Intel (Layout Designer) (480)554-5530

Aerospace Engineer

Tempe, AZ