USC NCG EE ASIC CAD Digital Circuit Analog Mixed Signal Verilog Hardware

April 1, 2009 To whom this may concern: I graduated from University of Southern California on May 15, 2009. I am currently looking for full-time, co-op, or internship related to ASIC design, Mixed-Signal Circuit, and CAD. I believe ASIC Engineer best suits my background. In Taiwan, I was a Cell Library engineer responsible for building Powerchip Semiconductor 0.15μm/0.18μm standard cell/IO library. In order to ensure the compatibility, I manipulated CAD tools and implemented ASIC deign flow which includes RTL(Verilog), Synthesis(Design Vision), Timing Analysis(PrimeTime), Place&Route&ECO(Astro), RC Extraction(StarRC), Physical Verification(Calibre, Hercules), Delay Calculation(Signal Storm). I also completed chip tape-out from shuttle15~shuttle18 and chip measurement to verify the function and timing of cell library. As a graduate student, I extended my skills to both digital circuit design which includes SRAM, DDS, CPU and DDR2 controller, and analog circuit design such as OPAMP and pipelined ADC. The enclosed file is my resume, which fully details my qualification for this position. I don’t mind traveling far for interview or doing unpaid internship. Thank you for your consideration. Sincerely, Ku-Tai Lin 1388 1/2 W 23rd ST., Los Angeles, CA 90007 kutailin@usc.edu

Electrical Engineer

Los Angeles, CA