Electrical Engineer Career Research and Resources
Grupo Antolin of Kentucky
In charge of running a production line.
Avg. Salary: $40,000 · Company Rank: Not Available
Hamilton Sundstrand / CDI Corporation
Lead the verification of an engine systems control FPGA. Designed an automated testbench generation tool in C++. Designed behavioral models of system components in C for use in the testbench. Implemented tests to verify the VHDL. Debugged the VHDL using ModelSim and Cygwin.
Avg. Salary: $95,000 · Company Rank: Not Available
Mediatek Inc. / Triple Crown Consulting
Contributed to the verification of a mobile multimedia processor. Wrote tests to debug the AXI and AHB bus fabric Verilog. Integrated the DSP RTL into the bus fabric.
Avg. Salary: $95,000 · Company Rank: Not Available
MIT Lincoln Labs / Apex Systems
Lead the design, implementation, verification and testing of a DVB-S2 Modem Transmitter. Demonstrated the working design in the lab to prove the design met all noise and functional specifications. Designed all of the non-3rd-party-IP VHDL including the complex signal mixer, direct digital synthesizer, RRC filter, physical layer framer, baseband processor and glue logic for the FEC and I/O. Designed a PLI- and FLI-based t...
Avg. Salary: $95,000 · Company Rank: Not Available
AMD (formerly ATI Technologies, Inc.)
Lead the verification of 2 Open GL 2.0-compliant 3D graphics texture processing units. Designed Verilog for the texture processing units. Designed the Verilog for Multi-Sample Anti-Aliasing (MSAA) textures in the Texture Cache block. Implemented C++ utilities for file I/O, data manipulation and test vector generation. Designed tests in C++ for texture formats, data packing, MSAA, vertex binning and culling. Debugged th...
Avg. Salary: $95,000 · Company Rank: Not Available
Mayflower Communications
Redesigned a GPS receiver in Verilog for faster operation, lower power consumption, bug fixes and additional functionality. Demonstrated the working design in the lab. Redesigned the anti-jam filter, FPGA processor interface, clocks & resets and removed redundant logic. Designed the data accumulation, storage and read-back block to meet new project specifications. Targeted the design to a Xilinx Virtex-2 4000 FPGA and a...
Avg. Salary: $95,000 · Company Rank: Not Available
Axiowave Networks
Defined inter-chip communication protocols. Contributed to the Quality-of-Service (QoS) specification. Lead the microarchitecture, design, verification and testing for 1 FPGA design. Created the microarchitecture for key components of 2 other FPGAs. Designed C++ functional models for the 3 FPGAs on the Switch Card as well as the full Switch Card. Demonstrated the working FPGA designs in the lab. Received 1 patent. De...
Avg. Salary: $95,000 · Company Rank: Not Available
ATI Technologies, Inc. (Now AMD)
Lead the design, verification, synthesis and timing of the color and pixel shaders for 2 ASICs. Lead the modeling, microarchitecture, design, verification, synthesis and timing of the world’s first widely available Z compression / decompression unit. Co-wrote a tool in C++ to optimize texture cache performance and configuration. Received 6 patents. Designed, verified, synthesized and timed VHDL and Verilog RTL for 2 ASI...
Avg. Salary: $95,000 · Company Rank: Not Available
Digital Equipment Corportation
Wrote tests to verify a 3D workstation graphics processor. Designed 2-D and 3-D random shape generators for the system test suite in C++. Integrated the 2-D and 3-D random shape generators into a unified random test generator.
Avg. Salary: $95,000 · Company Rank: Not Available
VSE Corp
Devise prognostic algorithms for Army JLENS radar system. Setup software development test lab servers and workstations.
Avg. Salary: $95,000 · Company Rank: 4.0 out of 5
