Mayflower Communications Work Values

Daily Duties at Mayflower Communications:

Redesigned a GPS receiver in Verilog for faster operation, lower power consumption, bug fixes and additional functionality. Demonstrated the working design in the lab. Redesigned the anti-jam filter, FPGA processor interface, clocks & resets and removed redundant logic. Designed the data accumulation, storage and read-back block to meet new project specifications. Targeted the design to a Xilinx Virtex-2 4000 FPGA and a 0.18µ Atmel SoC ASIC process. Synthesized and timed the design using multiple clock domains up to 60 MHz. Demonstrated the working design in the lab and designed the ASIC-specific features including the AMBA ASB ARM bus and DFT structures. Implemented a Verilog BFM and testbench to verify the ASIC features, plus creating the ASIC synthesis scripts.

What they like about Mayflower Communications:

Organizations with strong, centralized leadership are particularly attractive to you. You require a work environment with leadership that aggressively seeks to expand and grow the business and does so in a visible and decisive manner. In general you prefer to work in an environment in which there is a strong link between leadership, its actions, and a strong set of company-wide values.

Tags

ASIC, FPGA, C++, VHDL, verilog, Xilinx ISE

Skills

Verilog, VHDL, C++, C, Perl, PLI, FLI, Xilinx ISE, Synplify Pro, Design Compiler, ModelSim, VCS, Microsoft Visual Studio, gcc, g++, gdb, design modeling & architecture, RTL design & verification, FPGA & ASIC synthesis, place & route, floorplanning, formal verification, object oriented design

These are some of the questions we asked our climbers about their experiences with Mayflower Communications: