Mayflower Communications Work Values

Daily Duties at Mayflower Communications:

Redesigned a GPS receiver in Verilog for faster operation, lower power consumption, bug fixes and additional functionality. Demonstrated the working design in the lab. Redesigned the anti-jam filter, FPGA processor interface, clocks & resets and removed redundant logic. Designed the data accumulation, storage and read-back block to meet new project specifications. Targeted the design to a Xilinx Virtex-2 4000 FPGA and a 0.18µ Atmel SoC ASIC process. Synthesized and timed the design using multiple clock domains up to 60 MHz. Demonstrated the working design in the lab and designed the ASIC-specific features including the AMBA ASB ARM bus and DFT structures. Implemented a Verilog BFM and testbench to verify the ASIC features, plus creating the ASIC synthesis scripts.

What they like about Mayflower Communications:

You highly value a work environment built on a formal structure, rules, and regulations. You do not enjoy the unpredictability of shifting priorities and deadlines that upset your routine. You require and enjoy direction, input and accountability as part of your work environment. You have a strong need to participate in making key decisions and feel left out if your superiors or co-workers do not seek your input when making decisions. You thrive on providing good customer service to both internal or external customers, and doing so makes you feel good.

Tags

ASIC, FPGA, C++, VHDL, verilog, Xilinx ISE

Skills

Verilog, VHDL, C++, C, Perl, PLI, FLI, Xilinx ISE, Synplify Pro, Design Compiler, ModelSim, VCS, Microsoft Visual Studio, gcc, g++, gdb, design modeling & architecture, RTL design & verification, FPGA & ASIC synthesis, place & route, floorplanning, formal verification, object oriented design

These are some of the questions we asked our climbers about their experiences with Mayflower Communications: