Axiowave Networks Work Values

Daily Duties at Axiowave Networks:

Defined inter-chip communication protocols. Contributed to the Quality-of-Service (QoS) specification. Lead the microarchitecture, design, verification and testing for 1 FPGA design. Created the microarchitecture for key components of 2 other FPGAs. Designed C++ functional models for the 3 FPGAs on the Switch Card as well as the full Switch Card. Demonstrated the working FPGA designs in the lab. Received 1 patent. Designed data formats and communication protocols between the Ingress Traffic Manager (ITM) and Address Generator (AG), ITM and Distribution Chip (DC), and Line Card and ITM. Designed the ITM data formatting, address handling and data ordering and forwarding algorithms. Designed, debugged, synthesized, floorplanned and timed the ITM Verilog. Wrote tests in Perl to verify the ITM RTL. Targeted the ITM for a Xilinx Virtex-2 6000 FPGA at 125 MHz. Designed data flow algorithms for the ETM bandwidth manager and scheduler blocks. Wrote C++ models of the QoS system and contributed tweaks to the specification. Designed C++ models of the ITM, ETM and DC chips, and the Switch Card. Wrote tests in Perl to verify the C++ models. Fixed bugs in the processor command parser FPGA (BIF) so it would work in the lab. Created a specification language for programmable registers and software-accessible memories. Implemented a language parser in Perl that generated source code and documentation.

What they like about Axiowave Networks:

You give high priority to hiring firms with prestige. Market reputation and prestige of a firm may be determined through on-line research, and conversations with individuals working in your target industry. Note that firms "in the public eye" receive a great deal more critical publicity and attention than those operating with more anonymity. So as you assess your employment opportunities, be sure to seek out the positive aspects of the firm's reputation in addition to noting negative publicity the company may have received.

Tags

ASIC, FPGA, C++, VHDL, verilog, Xilinx ISE

Skills

Verilog, VHDL, C++, C, Perl, PLI, FLI, Xilinx ISE, Synplify Pro, Design Compiler, ModelSim, VCS, Microsoft Visual Studio, gcc, g++, gdb, design modeling & architecture, RTL design & verification, FPGA & ASIC synthesis, place & route, floorplanning, formal verification, object oriented design

These are some of the questions we asked our climbers about their experiences with Axiowave Networks: