CV, Curriculum Vitae and Online Resumes Search

---

Online Resumes with "tape out"

USC NCG EE ASIC CAD Digital Circuit Analog Mixed Signal Verilog Hardware

April 1, 2009 To whom this may concern: I graduated from University of Southern California on May 15, 2009. I am currently looking for full-time, co-op, or internship related to ASIC design, Mixed-Signal Circuit, and CAD. I believe ASIC Engineer best suits my background. In Taiwan, I was a Cell Library engineer responsible for building Powerchip Semiconductor 0.15μm/0.18μm standard cell/IO library. In order to ensure t...

Tags for this Online Resume: USC, NCG, EE, ASIC, CAD, Digital, Circuit, Analog, Mixed Signal, Verilog, Hardware, cadence, synopsys, Hspice, mentor, magma

Senior IC Mask Layout Designer w/ 25 years experience/Analog to Memory/ Team Leader

To continue with being a broad based help in facilitating the newest and fastest technologies down to 28nm from design through Tape Out. Have worked across the board with many of this industries best and brightest companies. To continue on this egalitarian path to assist start ups to established companies.

IC layout designer (mask designer)

As a layout designer, working for Wireless/RF mmWave design team. Main responsibilities include drawing high frequency RF ,Analog/mixed signal layout.Doing tape out. Working very closely with circuit designers and process engineers in development CDMA analog/mixed-signal chips, and high frequency wireless/ RF mmWave, Fbar filter chips in different processes like BiCMOS, GaAs, and Fbar. Duties include top-level down to circu...

Tags for this Online Resume: IC layout design, mask design, verification, DRC, LVS, tape out, BSEE, analog, RF, high speed, XOR, GDS, cds.lib, LayerMap

Engineer - 1 Years of Experience - Near 97229

Seeking an IC/CAD/SoC physical design engineering position QUALIFICATION * 16-year experiences in high-speed, low-power, billion-transistor, deep sub-micron CPU design * 3-yearexperience in sophisticated SoC design * Taped out 7 Intel CPU chips and 2 Broadcom communication chips

Tags for this Online Resume: Intel Co., Noise, Perl Programming Language, Sub-micron, Automation, Layout, Reliability, CAD flow, EDA tools, System engineering, synthesis, IRdrop/EM/ESD, STA, PnR, RC Extraction, CTS, Low power

Design Engineer

Summary of Qualifications: * Master of Science in Electrical Engineering from NYU-Polytechnic University in Brooklyn, New York * Created and developed a power estimate to create IR and EM correct power rails using Synopsys tools for TSMC flow. * Over 20 years as a physical designer and 10 tape-outs, from netlist to GDS Experienced with leading VLSI libraries: TSMC 90/65/20/28HP/14/10, Global Foundries 28HP and UMC 90 * Timi...

Tags for this Online Resume: Management, Project Management, VLSI, Cadence, Floorplanning, Documentation, Physical Verification, SOC, Tape-out, Compiler

Computer Programmer - 17 Years of Experience - Near 74129

Tags for this Online Resume: Chipset, Functional Testing, Intel Pentium microprocessor, Tape-out, Test, IC layout, Layout, C Programming Language, C Shell, Cadence, cadence

Electronic Drafter - 20 Years of Experience - Near 85224

CAREER SUMMARY * Master of integrated circuit layout design Extensive expertise and experience in layout floor planning, standard cell planning, hierarchical layout assembly, device matching, place and route of large digital and analog blocks, pad-ring, ESD clamps adjustment, post layout parasitic extraction and re-run timing/ power simulation, shielding and guard ringing, DFM, tape out GDSII format and E-beam mask generati...

Tags for this Online Resume: Layout, Cadence, Rf, Management, Wireless, Phase Lock Loop (PLL), PLL, Analog Circuit Design, Business Development, Circuit Design

Electronics Engineer

SUMMARY OF QUALIFICATION A Combination of specialized education and applied experience has resulted in excellent qualifications as a RF Design Engineer and Power Amplifier IC Design Engineer. Strong communication skills, interfacing effectively with clients and co-workers at all levels. Highly organized and analytical with well-developed technical design skills. Proficient at assessing requirements, setting priorities and i...

Tags for this Online Resume: Acceptance Testing, Amplifier, ANSYS, Cadence, Circuit Simulation, CMOS, Communication Skills, Data Management, Debugging, Engineering

Electronics Engineer - 12 Years of Experience - Near 94041

Profile: Experience in * Fullchip backend design integration, management, * Chip level edit, floor plaining and tapeout. * Analog and digital customer layout. * I/O PAD, memory full custom layout design including floor planning. * Has the certificate of the Cadence First and SOC Encounter * Using Laker tool generate the sub block automatically, and it's DRC and LVS. * Physical design, LVS, DRC and RC extraction and verifica...

Tags for this Online Resume: Layout, Management, Planning, Tape-out, Asic, Chip Design, Multimedia, CAD Tools, Cadence, Chip Verification

Electronics Engineer - 16 Years of Experience - Near 94041

Profile: Experience in * Fullchip backend design integration, management, * Chip level edit, floor plaining and tapeout. * Analog and digital customer layout. * I/O PAD, memory full custom layout design including floor planning. * Has the certificate of the Cadence First and SOC Encounter * Using Laker tool generate the sub block automatically, and it's DRC and LVS. * Physical design, LVS, DRC and RC extraction and verifica...

Tags for this Online Resume: Layout, Management, Planning, Asic, Chip Design, Multimedia, Tape-out, CAD Tools, Cadence, Chip Verification

Computer Hardware Engineer - 20 Years of Experience - Near 94087

Tags for this Online Resume: Dsp, DSPs, Macro (Predefined Code), Decoder, Ethernet, Tape-out, Asic, Logic Design, Microprocessors, FPGA