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Online Resumes with "RC Extraction"
USC NCG EE ASIC CAD Digital Circuit Analog Mixed Signal Verilog Hardware
April 1, 2009 To whom this may concern: I graduated from University of Southern California on May 15, 2009. I am currently looking for full-time, co-op, or internship related to ASIC design, Mixed-Signal Circuit, and CAD. I believe ASIC Engineer best suits my background. In Taiwan, I was a Cell Library engineer responsible for building Powerchip Semiconductor 0.15μm/0.18μm standard cell/IO library. In order to ensure t...
Tags for this Online Resume: USC, NCG, EE, ASIC, CAD, Digital, Circuit, Analog, Mixed Signal, Verilog, Hardware, cadence, synopsys, Hspice, mentor, magma
RESUME
Satish Chakkirala 1746 Ximeno Avenue, Apt # 5 Long Beach, CA - 90815 (714)-7944564 satish.0722@gmail.com OBJECTIVE An internship/full time position in the field of Electronics Engineering. Quest to work in a real professional environment, where I can enhance my skills and widen spectrum of knowledge. Also to make an indelible mark in the organization that i serve. Education •California State University Long beach...
Engineer - 1 Years of Experience - Near 97229
Seeking an IC/CAD/SoC physical design engineering position QUALIFICATION * 16-year experiences in high-speed, low-power, billion-transistor, deep sub-micron CPU design * 3-yearexperience in sophisticated SoC design * Taped out 7 Intel CPU chips and 2 Broadcom communication chips
Tags for this Online Resume: Intel Co., Noise, Perl Programming Language, Sub-micron, Automation, Layout, Reliability, CAD flow, EDA tools, System engineering, synthesis, IRdrop/EM/ESD, STA, PnR, RC Extraction, CTS, Low power
Electronics Engineer - 12 Years of Experience - Near 94041
Profile: Experience in * Fullchip backend design integration, management, * Chip level edit, floor plaining and tapeout. * Analog and digital customer layout. * I/O PAD, memory full custom layout design including floor planning. * Has the certificate of the Cadence First and SOC Encounter * Using Laker tool generate the sub block automatically, and it's DRC and LVS. * Physical design, LVS, DRC and RC extraction and verifica...
Tags for this Online Resume: Layout, Management, Planning, Tape-out, Asic, Chip Design, Multimedia, CAD Tools, Cadence, Chip Verification
Electronics Engineer - 16 Years of Experience - Near 94041
Profile: Experience in * Fullchip backend design integration, management, * Chip level edit, floor plaining and tapeout. * Analog and digital customer layout. * I/O PAD, memory full custom layout design including floor planning. * Has the certificate of the Cadence First and SOC Encounter * Using Laker tool generate the sub block automatically, and it's DRC and LVS. * Physical design, LVS, DRC and RC extraction and verifica...
Tags for this Online Resume: Layout, Management, Planning, Asic, Chip Design, Multimedia, Tape-out, CAD Tools, Cadence, Chip Verification
