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Online Resumes with "Tapeout"
USC NCG EE ASIC CAD Digital Circuit Analog Mixed Signal Verilog Hardware
April 1, 2009 To whom this may concern: I graduated from University of Southern California on May 15, 2009. I am currently looking for full-time, co-op, or internship related to ASIC design, Mixed-Signal Circuit, and CAD. I believe ASIC Engineer best suits my background. In Taiwan, I was a Cell Library engineer responsible for building Powerchip Semiconductor 0.15μm/0.18μm standard cell/IO library. In order to ensure t...
Tags for this Online Resume: USC, NCG, EE, ASIC, CAD, Digital, Circuit, Analog, Mixed Signal, Verilog, Hardware, cadence, synopsys, Hspice, mentor, magma
A motivated and enthusiastic ESD specialist/Analog IC Design engineer/Senior Device engineer with 16 years post graduate experience. Strong understanding of ESD/device/circuit/layout design, and semiconductor fabrication, having worked in top level ICs In
Shawn Tsui Address: Room501, BuildingNo.1, Lane 151, Donglan Road, Shanghai,P.R.China Zip code: 201100 Date of Birth: 09/08/1971 Marital status: Married Nationality: P.R. China Telephone: 86-21-64950511(20:00~22:00) Email: shawntsui@hotmail.com PROFILE: A motivated and enthusiastic Senior device engineer, a real ESD specialist, with 16 years post graduate experience.(B.Eng) Strong understanding...
Photomask Coordinator
My objective is to work in the semiconductor industry as a photomask coordinator in tapeout.
Tags for this Online Resume: semiconductor, photomasks, sql, synopsys, orders
SENIOR PROGRAM MANAGER, PROJECT CONSULTANT & PUZZLE SOLVER
Adaptive entrepreneurial results oriented leader with extensive experience utilizing Lean and Agile best practices while leading and collaborating with product managers, operations, business stakeholders, program managers, technically complex engineering teams, ODMs, and contract manufacturers to deliver customer-oriented, innovative, quality products. Experience includes rebuilding teams, delivering projects in resourc...
Ideal Companies: Small companies requiring expertise in Lean, Agile and scaling those frameworks as well as companies requiring leaders who can lead technologically complex, and diverse teams or projects in either operations, IT, or engineering.
Tags for this Online Resume: SaFE, Scaled Agile, Lean Framework, Program Management, Risk Management, Portfolio Management, SDLC, Collaboration and partnering with external partners, Integration, cross-functional development, operations, Leading projects in regulated industries, Planning, Schedules, Cross functional Team, Outsource Vendor management, Budgeting, Business and Project turn-around, Risk, Program, Product Life Cycle Management, NPV, ROI, COGs, strategy, business case development, Leading, ROHS, Standards, Best Practices
Design Engineer
Summary of Qualifications: * Master of Science in Electrical Engineering from NYU-Polytechnic University in Brooklyn, New York * Created and developed a power estimate to create IR and EM correct power rails using Synopsys tools for TSMC flow. * Over 20 years as a physical designer and 10 tape-outs, from netlist to GDS Experienced with leading VLSI libraries: TSMC 90/65/20/28HP/14/10, Global Foundries 28HP and UMC 90 * Timi...
Tags for this Online Resume: Management, Project Management, VLSI, Cadence, Floorplanning, Documentation, Physical Verification, SOC, Tape-out, Compiler
Electronics Engineer - 12 Years of Experience - Near 94041
Profile: Experience in * Fullchip backend design integration, management, * Chip level edit, floor plaining and tapeout. * Analog and digital customer layout. * I/O PAD, memory full custom layout design including floor planning. * Has the certificate of the Cadence First and SOC Encounter * Using Laker tool generate the sub block automatically, and it's DRC and LVS. * Physical design, LVS, DRC and RC extraction and verifica...
Tags for this Online Resume: Layout, Management, Planning, Tape-out, Asic, Chip Design, Multimedia, CAD Tools, Cadence, Chip Verification
Electronics Engineer - 16 Years of Experience - Near 94041
Profile: Experience in * Fullchip backend design integration, management, * Chip level edit, floor plaining and tapeout. * Analog and digital customer layout. * I/O PAD, memory full custom layout design including floor planning. * Has the certificate of the Cadence First and SOC Encounter * Using Laker tool generate the sub block automatically, and it's DRC and LVS. * Physical design, LVS, DRC and RC extraction and verifica...
Tags for this Online Resume: Layout, Management, Planning, Asic, Chip Design, Multimedia, Tape-out, CAD Tools, Cadence, Chip Verification
Manager - 18 Years of Experience - Near 95121
Seeking a challenging position in CAD Engineer.
Ideal Companies: Analog Devices
Tags for this Online Resume: CAD Tools, Foundry, CMOS, Fabrication, Tape-out, Debugging, HyperText Markup Language, Programming, Scheduling, Web
