A motivated and enthusiastic ESD specialist/Analog IC Design engineer/Senior Device engineer with 16 years post graduate experience. Strong understanding of ESD/device/circuit/layout design, and semiconductor fabrication, having worked in top level ICs In

Shawn Tsui Address: Room501, BuildingNo.1, Lane 151, Donglan Road, Shanghai,P.R.China Zip code: 201100 Date of Birth: 09/08/1971 Marital status: Married Nationality: P.R. China Telephone: 86-21-64950511(20:00~22:00) Email: shawntsui@hotmail.com PROFILE: A motivated and enthusiastic Senior device engineer, a real ESD specialist, with 16 years post graduate experience.(B.Eng) Strong understanding of ESD protection design and semiconductor device fabrication, having worked in a top level IC Research Institute and Analog IC design company in China. Seeking an ESD protection designer role with scope for technical challenge and career progression. EMPLOYMENT HISTORY 09/2002~Present Senior Device Engineer, ESD Specialist At a foreign funded analog IC design company in Shanghai Brought in by Company for ESD protection structure and Latch-up immunity design. · Setup ESD&Latch-up design rule for new process. · Develop ESD protection structures for new process and all products of company. · Hold the authority of finally check and sign for ESD & Latch-up immunity of all products before the GDS file tapeout. · Guide failure analysis and layout modification of products for ESD and latch-up issue. · Setup the device lab for device modeling, characterization and evaluation. · Guide the device team in new device development, characterization, modeling and evaluation. 07/1994~08/2002 Analog IC Design Engineer At an IC Research Institute of the National Information Industry Ministry, Brought in by Institute to design analog IC product. Role involves. · Design 4 projects (RF/IF amplifier, Low-Noise Wide-band Amplifier, High-speed operational Amplifier and Log Amplifier). · Set up an amplifier CAT system with programmable instruments. · Published 2 pieces of academic thesis on famous national publications. Tools supported include Cadence TECHNICAL SUMMARY · Solid experience of ESD protection design and latch-up immunity design on both device level and system level. · Solid understanding of Bipolar, CMOS, BiCMOS and BCD process · Device structure design and device modeling. · IC design methodology and CAD environment. · IC lab test and wafer test. · IC products debug and failure analysis. EDUCATION / TRAINING Education: 2003~2006 MEng. Microelectronics and Solid State Circuit, FuDan University Courses included Analogue IC design, VLSI, Semiconductor Device physics, Low power design, Digital Signal Processing, Semiconductor processing 1990~1994 BEng. Electronics, YuZhou University, Courses included Analogue circuit design, Digital circuit design, Digital Signal Processing, Communication principle, Microcomputer principle COURSES ATTENDED DURING EMPLOYMENT May 2007 Advanced ESD protection Aug 2006 Semiconductor Device Physics June 1998 ISO9001 quality identification July 1996 technology introduced from Russia Sep 1995 Cadence system operating. PERSONAL · Gain an award of excellent papers from the 8th Youth Annual Conference of Chinese Institute of Electronics-CIE, Aug 2002 · Gain the 2nd pride award from China Electronics Technology Group Corp. (CETC), May 2004. · Gain the 2nd pride award from The Commission of Science Technology and Industry for National Defense, Nov 2004. · Gain 2 patents, Nov 2004 · Sports: Running, soccer

Aerospace Engineer