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Online Resumes with "Synopsys VCS"



ASIC/SoC design engineer

To excel in the field of ASIC/SoC engineering and work in a challenging work environment and contribute positively to the growth of the technology industry.

Tags for this Online Resume: ASIC design engineer, synopsys VCS, verilog HDL, System Verilog , SVA, C++, CADENCE , schematic entry, layout, PLL, USB, AMBA, system on chip design

To work in a challenging environment, where I can effectively utilize my skills, knowledge, experience and potential towards the growth of the organization.

Professional Experience: Working as Member of Technical Staff at PW systems/Ichip Technologies, Hyderabad from Oct 2008 to till date. Worked as Verification Engineer at StellarIP Solutions, Hyderabad from Feb 2007 to Sep 2008. Got Cadence EDA tools Experience for Full Custom ASIC Design while doing Advanced PG Diploma in VLSI design in VEDANT, Chandigarh certified by Semiconductor Complex Ltd under Cadence Universi...

Ideal Companies: synopsys, cadence, AMD, Cisco, Wipro

Tags for this Online Resume: VLSI design Tools Simulation: ModelSim, Synopsys VCS, Cadence NC-Sim Implementation: Xilinx ISE 9.1i Tools: Specman, NC-Verilog, Vbuilder, Leonardo- Spectrum, ICFB (Spectre, Virtuoso, Assura), SOC Encounter, Co-ware Processor. Skills

Electronics Engineer

I wish to start a VLSI company for that i have choosed ME-VLSI design at that time of my PG i have learned lot of things about VLSI. me and my friends discussed more and more about design flow which is not enough for starting a company so i need some experience for learning about VLSI industries and getting more knowledge in this field.

Tags for this Online Resume: Verilog, VHDL, C,C , Xilinx ISE, ModelSim, Synopsys(VCS,DESIGN COMPILER,PRIME TIME), QUESTASIM

Electrical Engineer - Graduated 2017 - Near 95051

Actively seeking an opportunity in the field of VLSI where I can put my engineering skills into practice & develop myself along with the development of the organization. ACADEMICS: * MS in Electrical Engineering GPA: 3.350 San Jose State University, San Jose, CA August 2015 - May 2017 Related Coursework: Logic Design for DSP/Communication, Advanced Logic Design, Probability- Random Variables and Stochastic Process, Advanced...

Tags for this Online Resume: Automation, Documentation, Failure Analysis, Troubleshooting, VLSI, SoC Design, UVM, Cadence, RTL design/ Verification, ASIC, Verilog, SystemVerilog, VHDL, Python

Featured Profile

ASIC/SoC/FPGA Digital Design and Verification Engineer - 2 Years of Experience in ASIC Design and 1 Year experience in Verification Domain- Near 95825

Seeking Full-Time/Internship in ASIC/SoC Design Verification/Validation/FPGA. Two years hands on Experience in RTL design and 1 year experience in Verification, including RTL Design, Verilog HDL/ System Verilog, UVM, Code Coverage, Static Timing Analysis (STA), Functional Coverage, Assertions.

Ideal Companies: Intel, Synopsys, Xilinx, NXP, ASIC North, Segate, Mentor Graphics, Ericssion, Qlogic, Marvell, Qualcomm, Nvidia, RADIANSYS, EncoreSemi, Cirrus Logic, ARM, IBM, HCL, Amiga Infotech, L&T, CISCO, Synaptics, AMD, Broadcomm, CTG, Ambrella, Micron, Microchip, Cybercoders, OSI Semiconductors, Google, Microsoft, Facebook, Western Digital, Global Foundries, jma wIRELESS

Tags for this Online Resume: C++ Programming Language, Cadence, Coding, Compiler, Cyclic Redundancy Code (CRC), FPGA, Graphic Design, Linux, Matlab, SoC, CDC, UVM, Code Coverage, Functional Coverage, System Verilog Assertions (SVA), RTL, CMOS, System Verilog, Self checking, Constrained random teatbench, Direct Testbench, Xilinx Spartan 3E FPGA, PERL/ tcl, : Linux, Unix, Windows, Mac, DVS Protocol, MESI Protocol, UART, SPI, DDR, PCI, PCIe(Begineer), Concept of Pipeline and Hazards, Addressing Mode, Cache, Cache Mapping, Virtual Memory, Paging, DMA, ASIC, Synopsys VCS, QuestaSim, ModelSim Simulator Mentor Graphics, Cadence Virtuoso, Design Compiler, Cadence Pspice, Xilinx ISE, Simulink, EDA Playground, C++, Object Oriented Programming, LVS, DRC