Actively seeking an opportunity in the field of VLSI where I can put my engineering skills into practice & develop myself along with the development of the organization. ACADEMICS: * MS in Electrical Engineering GPA: 3.350 San Jose State University, San Jose, CA August 2015 - May 2017 Related Coursework: Logic Design for DSP/Communication, Advanced Logic Design, Probability- Random Variables and Stochastic Process, Advanced Computer Architecture, Digital System Design, SOC Design and Verification, ASIC CMOS Design, High Speed CMOS Circuits, Verification using UVM methodology. * Bachelor of Engineering in Electrical Engineering GPA: 3.860 Gujarat Technological University, India June 2011 - May 2015 TECHNICAL PROFICIENCY: * Basics of C, Python, Matlab, Simulink with both Windows/UNIX environments. * RTL design, debug and timing simulations. * Programmable Logic and FPGA architecture. * AMBA AXI, AHB, APB, UART, UVM * Basics of PLC Ladder Programming. * VHDL/Verilog Design, SystemVerilog assertions, Verification. * Cadence tools Virtuoso and Assura. * Verilog synthesis, placement and routing and debugging using Synopsys VCS and analysis using design vision.

Highlights:

• Automation
• Documentation
• Failure Analysis
• Troubleshooting
• VLSI
• SoC Design
• UVM
• Cadence
• RTL design/ Verification
• ASIC
• Verilog
• SystemVerilog
• VHDL
• Python