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Online Resumes with "LVS "
Sr. Analog/Mixed Signal IC Design Engineer
looking for a Sr. Engineer position with a growing company in the field of eletronics engineer.
Tags for this Online Resume: cmos,transistor level,noise, matlab,hspice,spectreRF,hsim, Cadence,Mentor Graphics,Unix, pll,dll,d/a,real-time osc,bangap,op-amp,ldo,sram, layout,drc,lvs,extration, test,probing,characterization,debug
Mask Design Consultant with 12 years experience looking to help get your jobs done.
I'm looking to do mask design work using Cadence Virtuoso drawing tools and Calibre or Hercules verification of DRC and LVS. I have excellent experience in both analog and digital environments.
Ideal Companies: Any Semiconductor company
Tags for this Online Resume: Cadence, Virtuoso, Calibre, Hercules, Experienced, Unix, DRC, LVS
chip design expert
Ideal Companies: intel pasemi
Tags for this Online Resume: cmos, bicmos, cadence, vlsi, drc, lvs, calibre, sige
ASIC Layou / IC layout / IC Mask design or CAD
C or PCB Design & Drafting, testing IC chips
Tags for this Online Resume: Cadence, Analog, Digtal, DRC, LVS, Schematic
Senior Layout Mask Designer
To whom it may concern, My name is Le Tran and I would like to be considered for the Senior IC Layout Designer position. I am confident that I am a strong candidate for this position because of my 9 + years of experience at Lattice Semiconductor as an IC Layout Designer. At Lattice, and two and haft year consultant with Analog Device until now . I was responsible but not limitied to full chip and full block layout includ...
IC layout designer (mask designer)
As a layout designer, working for Wireless/RF mmWave design team. Main responsibilities include drawing high frequency RF ,Analog/mixed signal layout.Doing tape out. Working very closely with circuit designers and process engineers in development CDMA analog/mixed-signal chips, and high frequency wireless/ RF mmWave, Fbar filter chips in different processes like BiCMOS, GaAs, and Fbar. Duties include top-level down to circu...
Tags for this Online Resume: IC layout design, mask design, verification, DRC, LVS, tape out, BSEE, analog, RF, high speed, XOR, GDS, cds.lib, LayerMap
resume
Zhengdong Fan 1215 E Vista Del Cerro, APT2022, Tempe, US, AZ, 85281 480-334-6886 zfan6@asu.edu Objective Look for Full Time Job related with: Analog/RF,Digital, Mix-signal IC design, application, analysis or product Education M.S.E of Engineering in Electrical Engineering of Arizona State University (ASU), Tempe,AZ Specialty area: Electronic and Mixed Signal Circuits May.2010 GPA 3.32 B.E. in Electronic...
Digital Design Engineer
Looking for an opportunity to work on ASIC, Digital design and Verification in a professional environment, enrich competencies and endeavor towards fulfillment of the vision of the organization and to make the best use of engineering and interpersonal skills in a challenging field
Ideal Companies: Cadence, Mentor Graphics, Kodak, Texas Instruments, EMC2, Intel, Qualcomm, Broadcom
Tags for this Online Resume: Cadence, Mentor, Team Player, Digital Design, DRC, LVS, ASIC, FPGA, VLSI, VHDL, Verilog, C, TCL
RESUME
Satish Chakkirala 1746 Ximeno Avenue, Apt # 5 Long Beach, CA - 90815 (714)-7944564 satish.0722@gmail.com OBJECTIVE An internship/full time position in the field of Electronics Engineering. Quest to work in a real professional environment, where I can enhance my skills and widen spectrum of knowledge. Also to make an indelible mark in the organization that i serve. Education •California State University Long beach...
Senior Staff CAD/EDA engineer, San Jose
To pursue a challenging IC CAD Engineering position involving design process development, methodology assessment, integration and support of vendor and internal EDA applications and flows, custom EDA development, support for front-end, back-end, and front to back for IC projects by utilizing my twenty three years of experience in the Analog/RF/Digital/Memory IC Design industry .
Tags for this Online Resume: EDA/CAD design, PDK development in Cadence Virtuoso, Rule deck development for DRC, LVS & Extraction, Pcell & Application development in skill & ROD, Custom Virtuoso & ADE development , EDA devolopment and support from front to back-end for Analog/RF/Digital/Memory IC design
CAD Engineer
I would like to support Semiconductor Design teams, automating processes, using SKILL for Cadence and Shell scripts. Also environment support such as licenses, LSF, installation and set up of PDKs and libraries.
Ideal Companies: Startup or small seminconductor companies
Analog mask layout
Tags for this Online Resume: Cadence Virtuoso, Assura Calibre, DRC LVS, analog layout, custom design, ADC DAC PLL VCO LDO, custom mask design
