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Zhengdong Fan 1215 E Vista Del Cerro, APT2022, Tempe, US, AZ, 85281 480-334-6886 zfan6@asu.edu Objective Look for Full Time Job related with: Analog/RF,Digital, Mix-signal IC design, application, analysis or product Education M.S.E of Engineering in Electrical Engineering of Arizona State University (ASU), Tempe,AZ Specialty area: Electronic and Mixed Signal Circuits May.2010 GPA 3.32 B.E. in Electronics and Information Engineering of Huazhong University of Science and Technology (HUST), Wuhan, China June.2008 GPA 3.2 Skills .CAD Tool: Cadence (spectre, spectreRF, Virtuoso Layout Editor), ADS .Software Environments: Matlab, Simulink, Verilog, ModelSim, C++, .Development Kits: TI Code Composer Studio(TI TMS320C55x DSP, MSP430 Microcontroller), Metroworks CodeWarrior(Freescale DSP 56858EVM) Projects Analog: .4th order switched-capacitor cascaded Elliptic bandpass filter for a VLSI single-chip 1200-bps CMOS minimum shift keying (MSK) wireless receiver, 0.5um AMI CMOS process. .Switched-Cap charge-pump DC/DC converter from 0.5V to 1.5V for solar cell application. .VLSI Polyphase filter design constructed from 5th order lowpass Butterworth filter of 100kH –3dB bandwidth through a 100 kHz frequency shift for VLSI integrated RF receiver system. .70dB gain, 600MHz bandwidth OTA with switched-capacitor common-mode feedback. Mix-Signal: .Team of 4 in designing a 10-bit 30Ms/s pipeline ADC implemented using 2.5 bit/stage pipeline stages as the first four stages and 3 bit Flash ADC as the last stage; also designed fully-differential OTA and comparators, switched-capacitor flip-over MDAC, and Digital Control Logic(ie. Decoder, residue recombination logic, switch control logic). .Designed and simulated 3rd order hybrid feedforward-feedback (CIFF and CIFB) continuous-time Sigma-Delta AD modulator using 3-bit quantizer and NRZ DAC to achieve performance of 72dB SNDR, 12-bits ENOB, and 10MHz input bandwidth sampled at 16 OSR. The system level design was first characterized in Matlab and then the transistor level blocks designed in Cadence. RF: .GSM900 direct conversion front-end receiver design with overall performance of 22dB Gain, 5.4dB Noise Figure,-14dBm IIP3, 60mW power consumption implemented in TSMC 0.35um technology using common-source inductor-degeneration LNA with 14dB gain, 0.35dB Noise Figure, -7.2dBm IIP3, Gilbert cell mixer with 12.4dB Conv. Gain, 7.2dB Noise Figure 1.6dBm IIP3 and inter-stage impedance matching network.First did the system level link budget simulation in ADS then the transistor level circuit design and simulation in Cadence Digital: ..32 channel Data Processing System including 32 serial to parallel data converter, five 32-bit FIFO Memory, Header Decoder, 32 bit: Ripple Carry Adder with pipeline, Barrel Shifter, Multiplier using dynamic logic family and glue logic. Optimized the transistor size and layout design. ..16 bit Carry Select (square root) Adder design all through simulation, layout, DRC, extraction, LVS, and post layout simulation. ..Digital clock with Annual Calendar design on Altera FPGA Senior Design: .Team of 3 at ASU with Prof. James T. Aberle from January 2008 to December 2008: .Bike Anti-theft System with RFID recognition, implemented with Manchester code decoding algorithm and interfaced with user through USB port. This project is designed using TI MSP430 MCU. Award Analog Design Winner at Texas Instruments .Senior Design at ASU 2009 Experience Research Assistant at Internet Technology and Engineering R&D Center of HUST (Key Laboratory of China) .2 Month Internship from July 2007 to August 2007. .Responsible in figuring out various ways of improving the stability of mainframe servers. .Researched in improving the security and reliability of Session Initiation Protocol server (VOIP protocol) using cluster architecture

Electrical Engineer

Tempe, AZ