Verifast Yechnologies Work Values

Daily Duties at Verifast Yechnologies:

High- intensity verification training called Jumpstart ASIC Verification, training in Verification Architecture, Functional Verification, Test bench development, Scripting Code & automation. Writing direct testbench, self-checking testbench, constrained random testbench in Verilog/ System Verilog, designing in RTL. Generated multiple test cases and launched Regression, compared multiple test cases and if it passes then rerun the script to analyze the results

What they like about Verifast Yechnologies:

The social vibrance of a hiring firm is very important to you. Your ability to make and maintain friendships there is a critical part of your decision. You would likely be dissatisfied with a workplace that is quiet, cold, or otherwise not particularly social. When you investigate a new hiring company, ask recruiters, managers, and potential co-workers about the social life and opportunities there. This is especially important when you are relocating; moving dramatically alters your social sphere both inside and outside the workplace.

Tags

C++ Programming Language, Cadence, Coding, Compiler, Cyclic Redundancy Code (CRC), FPGA, Graphic Design, Linux, Matlab, SoC, CDC, UVM, Code Coverage, Functional Coverage, System Verilog Assertions (SVA), RTL, CMOS, System Verilog, Self checking, Constrained random teatbench, Direct Testbench, Xilinx Spartan 3E FPGA, PERL/ tcl, : Linux, Unix, Windows, Mac, DVS Protocol, MESI Protocol, UART, SPI, DDR, PCI, PCIe(Begineer), Concept of Pipeline and Hazards, Addressing Mode, Cache, Cache Mapping, Virtual Memory, Paging, DMA, ASIC, Synopsys VCS, QuestaSim, ModelSim Simulator Mentor Graphics, Cadence Virtuoso, Design Compiler, Cadence Pspice, Xilinx ISE, Simulink, EDA Playground, C++, Object Oriented Programming, LVS, DRC

Skills

• Language: Verilog HDL, System Verilog, C++, Object Oriented Programming, • Verification Methodologies: UVM, • Scripting Language: PERL/ tcl , • Hardware: Xilinx Spartan 3E FPGA, Arduino Development Board, • Tools: Synopsys VCS, QuestaSim, ModelSim Simulator Mentor Graphics, Cadence Virtuoso, Design Compiler, Cadence Pspice, Xilinx ISE, MATLAB, Simulink, EDA Playground, • Operating System: Linux, Unix, Windows, Mac, • Protocols: DVS, MESI, UART, SPI, DDR, PCI, PCIe (Beginner), • Architecture: Concept of Pipeline and Hazards, Addressing Mode, Cache, Cache Mapping, Virtual Memory, Paging, DMA

These are some of the questions we asked our climbers about their experiences with Verifast Yechnologies: