CV, Curriculum Vitae and Online Resumes Search
Recruiters - Try Postings!
Postings.com™ is a must-have for recruiters who want to:
- Find Qualified Candidates
- Find Job orders and Post Splits
- Be Found in Search Engines
- Implement a Social Sourcing Strategy
Job Seekers - Look Here!
Hitting a wall with your job search? Try Climber Premium.
- Top the Search Engines
- Unsurpassed Candidate Marketing
- Power Career Networking
- Fresh Jobs from the Net
Were you looking for QuestaSim job results?
Click Here to search for QuestaSim in our 2.4M jobs.
Online Resumes with "QuestaSim"
I wish to start a VLSI company for that i have choosed ME-VLSI design at that time of my PG i have learned lot of things about VLSI. me and my friends discussed more and more about design flow which is not enough for starting a company so i need some experience for learning about VLSI industries and getting more knowledge in this field.
ASIC/SoC/FPGA Digital Design and Verification Engineer - 2 Years of Experience in ASIC Design and 1 Year experience in Verification Domain- Near 95825
Seeking Full-Time/Internship in ASIC/SoC Design Verification/Validation/FPGA. Two years hands on Experience in RTL design and 1 year experience in Verification, including RTL Design, Verilog HDL/ System Verilog, UVM, Code Coverage, Static Timing Analysis (STA), Functional Coverage, Assertions.
Ideal Companies: Intel, Synopsys, Xilinx, NXP, ASIC North, Segate, Mentor Graphics, Ericssion, Qlogic, Marvell, Qualcomm, Nvidia, RADIANSYS, EncoreSemi, Cirrus Logic, ARM, IBM, HCL, Amiga Infotech, L&T, CISCO, Synaptics, AMD, Broadcomm, CTG, Ambrella, Micron, Microchip, Cybercoders, OSI Semiconductors, Google, Microsoft, Facebook, Western Digital, Global Foundries, jma wIRELESS
Tags for this Online Resume: C++ Programming Language, Cadence, Coding, Compiler, Cyclic Redundancy Code (CRC), FPGA, Graphic Design, Linux, Matlab, SoC, CDC, UVM, Code Coverage, Functional Coverage, System Verilog Assertions (SVA), RTL, CMOS, System Verilog, Self checking, Constrained random teatbench, Direct Testbench, Xilinx Spartan 3E FPGA, PERL/ tcl, : Linux, Unix, Windows, Mac, DVS Protocol, MESI Protocol, UART, SPI, DDR, PCI, PCIe(Begineer), Concept of Pipeline and Hazards, Addressing Mode, Cache, Cache Mapping, Virtual Memory, Paging, DMA, ASIC, Synopsys VCS, QuestaSim, ModelSim Simulator Mentor Graphics, Cadence Virtuoso, Design Compiler, Cadence Pspice, Xilinx ISE, Simulink, EDA Playground, C++, Object Oriented Programming, LVS, DRC