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Online Resumes with "OVM UVM"
Senior Level ASIC and FPGA chip design verification engineer - 20+ years experience OVM/UVM
I am seeking the ASIC or FPGA Design Verification Engineer position. I can offer extensive experience in Verilog, System Verilog or VHDL verification and design, OVM/UVM verification environments, synthesis, timing, and ATPG from start of concept to their release to physical design. I have built up OVM and SystemVerilog test environments from scratch. I have bus Interface skills in design, verification, and debug: SAS and ...
Tags for this Online Resume: Design, Verification, ASIC, OVM/UVM, SystemVerilog, FPGA, SAS/SATA
Developer
Tags for this Online Resume: Verilog, System Verilog, OVM UVM, Verification, Semiconductor, FPGA, Veloce
Electrical Engineer - 3 Years of Experience - Near 77025
SUMMARY: * Knowledge of semiconductor device physics, process technology, and design rules. * Proven ability in hardware Design with Cadence (Virtuoso layout, OrCAD, VIP, Design IP) * Design & Verification with Verilog, system Verilog & OVM/UVM methodologies. * Proficient C, C++, python and MATLAB programming skills & Tools experience with Altera Quartus, Modelsim, Silvaco Virtual Wafer Fab, MATLAB, Proteas, LTspice, LINUX.
Tags for this Online Resume: FPGA, Programming, VERILOG, Asic, C Programming Language, C++ Programming Language, Cadence, Electronics, Embedded Systems, Matlab
Electrical Engineer - 1 Years of Experience - Willing to relocate anywhere
To secure a full-time position in the field of Electrical and Electronics Engineering allowing me to use my technical skills and abilities towards the growth of the organization while gaining valuable experience
Tags for this Online Resume: Altera, Autocad, Autodesk AutoCAD, C Programming Language, C++ Programming Language, Cadence, Code Analysis, Coding, Engineering, electrical, hardware, embedded, synopsys, VHDL, Verilog, System Verilog, Matlab, labVIEW, Python, Perl, OVM/UVM
