Looking for Senior Staff CMOS RF/Analog IC Design Engineer or Technical IC Design Manager
Micro-Electronics Engineering.
IC Digital&Analog CMOS,BCMOS mix-signal Design.
DRC and LVS,ERC Chip planning Block cell level and Standar Libaries cell. Used Mentor Garphic or Cadence CAD Tools to make chip plan.
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Team work player., Meet the timing to the market, Customer sactifaction's, Following the leader, New Design Teachinical's, Exprience of Teachinical Design
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Cadence, VLSI, ASIC, DRC, LVS, Analog Layout Design, Digital , Mixed Signal, Verification, CMOS, EM, Calibre, K2, , Senior Engineer
A mixed signal IC designer with ten years experience in the field of consumer / medical / scientific / industrial imaging devices(mainly CMOS and CCD). Experienced at block level and system level imager design from conception through silicon. Ability to work well as both an individual contributor or group member. Adept at working in cross functional teams to come up with working solutions for difficult problems.
Ideal Companies: foveon, aptina, omnivision, hynix, sony, Fairchild Imaging
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imaging, imager, sensor, design
Looking for a Product Engineering, Failure Analysis, or Reliability/QA Engineering position, which offers opportunities to increase my responsibilities and advancement in Semiconductor, Solar or Saving Energy Field.
Ideal Companies: Intel, Advanced Device Inc (ADI), Cicco, Maxim, Analog Semiconductor Com
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Semiconductor Engineer
I am an experienced IC designer in both CMOS and Bipolar device level circuit design. I have experience as a Design manager, Project Manager, and Design Lead. I have participated in every level of chip design from concept and process selection, through design, to final test and product engineering.
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project manager, design manager, ic design, ic design, SERDES, SERDES, device level design, device level design, cmos, cmos, bipolar, bipolar, Certified PMP
I have experience in Analog, Bipolar and CMOS Digital design. I am fluent with Cadence VXL, Calibre LVS, Calibre DRC and Hercules DRC and LVS. Experienced with the Pulsic Router for digital standard cell routing.
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Mask Layout, Mask Design, Layout Design, Photomask Layout, Phjotomask Design
: Over 19 years of CMOS design experience concentrated in 100 plus SONET
and BROADBAND ASIC architectures. The scope of ASIC design comprised PD,
digital test, functional & topological verification, DFT - test insertion, timing
closure via STA & vector simulation, and SI. Strong analytical and result oriented
objectives emphasizing development and execution. Skill...
