Experience in * Fullchip backend design integration, management, * Chip level edit, floor plaining and tapeout. Includingfull chip DRC/LVS, and antenna violations at all levels of the design * Analog and digital customer layout. * I/O PAD, SRAM and D-Ram memory full custom layout design including floor planning. * Has the certificate of the Cadence First and SOC Encounter * Using Cadence Mentor Graphics and generate the sub block automatically, and it's DRC and LVS. Performing DRC/LVS and RC extraction, * Physical design, LVS, DRC and RC extraction and verification. * Cadence Tools Virtuoso, Opus, edge, Hspice and Assura, Dracula, etc.. * Cache related circuit design. CAD environment setup, and back end team setup in china. * Familiarity tools, such as Cadence tools: Virtuoso, Dracula, cdl netlist, Hspice, SOC encounter * Synopsys: Pathmill, Arcadia, and timill (EPIC tools) * Metor Graphics: Calibre, Excabre
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