Summary Principal ASIC Design Engineer with more than 20+ years ASIC design and verification experience including completion of more than 10 project cycles from concept through successful first-pass production release of silicon. Experience includes all aspects of ASIC design and verification, including writing micro-architecture specifications, Block Level and Subsystem design and verification, Timing closure, FPGA design and debug, Lint and Formal Verification. Extensive deep sub-micron experience (to 10nm FinFET) technologies. Was the Processor lead responsible for the integration of 11 embedded ARM processors and interconnect IP. Personally designed all processor slaves including an AMBA to NAND Flash interface, an AMBA to DMA units, an AMBA to streaming SRAM style RDY based interface, AMBA to Register, and AMBA to UART interface. Known for taking ownership and doing what it takes to get the work done well and on time.

Highlights:

• Asic
• ASIC Design
• ARM
• ASIC Design and Verification
• Associate in Risk Management
• Chip Design
• Coding
• Debugging
• Deep Sub-Micron
• Digital Design
• FPGA