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Online Resumes with "static timing analysis"
ASIC Physical Design Engineer- Certified- GPA: 4/4
Responsible for Physical Design Engineering like Floor planning, Static timing Analysis, Placement and Routing, Layout Design.
RESUME
Satish Chakkirala 1746 Ximeno Avenue, Apt # 5 Long Beach, CA - 90815 (714)-7944564 satish.0722@gmail.com OBJECTIVE An internship/full time position in the field of Electronics Engineering. Quest to work in a real professional environment, where I can enhance my skills and widen spectrum of knowledge. Also to make an indelible mark in the organization that i serve. Education •California State University Long beach...
Application Engineer
To work in a design company where my ASIC knowledge can be utilized for the growth of the organization and self
Tags for this Online Resume: ASIC design , synthesis , static timing analysis , Analog , digital , support
Component Design Engineer - 3 years experience - Intel, Folsom
I am a design engineer who has 3 years of work experience in Hardware Design-functional verification, static timing analysis, floor planning, Place and Route, design optimization, power and noise analysis, circuit quality, register file array and data path block closure flows, custom bottom up register file build
Electronics Engineer - 15 Years of Experience - Near 95014
ASIC PHYSICAL DESIGN ENGINEER Dedicated team player and tenacious problem solver with 15 years of experience. Extensive Hardware, Software, ASIC and VLSI Design background in Synthesis, Static Timing Analysis, Formal Verification, Place&Route, and SoC IP integration. Extensive experience in scripting with PERL, C, TCL, CSH, and Synopsys Tools.
Ideal Companies: no interviews no offers
Tags for this Online Resume: San Jose, ICC, PERL, PrimeTime, Redhawk, Calibre, Tweaker, Parasitic Extraction, Asic, ASIC Design
Product Design Engineer
Perform the following tasks such as writing Design and Development RTL coding/fixing Simulation Sythesis Lint checking Clock Domain Crossing (CDC) Analysis Scan insertion for DFT Formal Verification Floorplanning Power Planning Place & Route LVS/DRC/Antenna clean final sign-off using for Static Timing Analysis (STA) Power Analysis Integration for Cluster level & Toplevel and also resolving SI issues for the following compan...
Tags for this Online Resume: Crosstalk (Comm Sw), Asic, ASIC Design, Prime, Test, Altera, C++ Programming Language, C/C++ Programming Languages, Dsp, DSPs
