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Online Resumes with "LVS DRC"
Mask Design Consultant with 12 years experience looking to help get your jobs done.
I'm looking to do mask design work using Cadence Virtuoso drawing tools and Calibre or Hercules verification of DRC and LVS. I have excellent experience in both analog and digital environments.
Ideal Companies: Any Semiconductor company
Tags for this Online Resume: Cadence, Virtuoso, Calibre, Hercules, Experienced, Unix, DRC, LVS
CAD Engineer
I would like to support Semiconductor Design teams, automating processes, using SKILL for Cadence and Shell scripts. Also environment support such as licenses, LSF, installation and set up of PDKs and libraries.
Ideal Companies: Startup or small seminconductor companies
Computer Hardware Engineer - 3 Years of Experience - Near 95131
SUMMARY I've been working in layout / auto P&R field for almost 18 years and with strong background on the back-end side. I've also been working on timing driven P&R for the last 10 years.
Tags for this Online Resume: CAD Tools, Layout, Cadence, Layout Design, LVS/DRC, Floorplanning, icc
Product Design Engineer
Perform the following tasks such as writing Design and Development RTL coding/fixing Simulation Sythesis Lint checking Clock Domain Crossing (CDC) Analysis Scan insertion for DFT Formal Verification Floorplanning Power Planning Place & Route LVS/DRC/Antenna clean final sign-off using for Static Timing Analysis (STA) Power Analysis Integration for Cluster level & Toplevel and also resolving SI issues for the following compan...
Tags for this Online Resume: Crosstalk (Comm Sw), Asic, ASIC Design, Prime, Test, Altera, C++ Programming Language, C/C++ Programming Languages, Dsp, DSPs
Electronics Engineer - 12 Years of Experience - Near 94041
Profile: Experience in * Fullchip backend design integration, management, * Chip level edit, floor plaining and tapeout. * Analog and digital customer layout. * I/O PAD, memory full custom layout design including floor planning. * Has the certificate of the Cadence First and SOC Encounter * Using Laker tool generate the sub block automatically, and it's DRC and LVS. * Physical design, LVS, DRC and RC extraction and verifica...
Tags for this Online Resume: Layout, Management, Planning, Tape-out, Asic, Chip Design, Multimedia, CAD Tools, Cadence, Chip Verification
Electronics Engineer - 16 Years of Experience - Near 94041
Profile: Experience in * Fullchip backend design integration, management, * Chip level edit, floor plaining and tapeout. * Analog and digital customer layout. * I/O PAD, memory full custom layout design including floor planning. * Has the certificate of the Cadence First and SOC Encounter * Using Laker tool generate the sub block automatically, and it's DRC and LVS. * Physical design, LVS, DRC and RC extraction and verifica...
Tags for this Online Resume: Layout, Management, Planning, Asic, Chip Design, Multimedia, Tape-out, CAD Tools, Cadence, Chip Verification
