Challenging position in SOC implementation. Relevant Professional Skills - Hands-on EDA tool experience Block-level floorplanning and clock tree synthesis using ICC. Timing and congestion analysis using IC Compiler (ICC), Physical Compiler and Astro. ECO methodology, Timing Closure using IC compiler and Prime Time. Place & Route Design Automation using ICC and scripts (cshell, perl, tcl and scheme code) Automated design library/collateral view generation using ICC and Cadence Virtuoso. Block-level and chip-level layout verification using nettran, Hercules and Calibre. Other EDA/tools Avanti Suite (Planet, Saturn, Apollo), Cadence Suite (Virtuoso, SE), Intel's Athena Environment, AutoCAD, Assembler, Fortran, Matlab

Highlights:

• Management
• Physical Verification
• Cadence
• Intel
• Layout
• Apollo
• Cellular
• Data Management
• Integrate
• Packaging