COMPANY	POSITION HELD	DATES WORKED
(Confidential)	(Confidential)	3/2000 - Present
Intel Corp	(Confidential)	2/1996 - 3/2000

SCHOOL	MAJOR	YEAR	DEGREE
UCLA	Electrical Engineering	1995	Bachelor Degree

Highlights:

Responsible for circuit design of integer register file for Intel's 1st Itanium project. Responsible for logic design of pipeline control, execution control, and cache subsystem for 3 generations of RISC processor at Avalent. Responsible for logic design of DMA, SDRAM Controller, Serial Comm Interface (SCI) blocks at Avalent. Developed synthesis and place and route methodology for Avalent.

Companies I like:

Trident Sigma Apple

P&L responsibilities
Presentation
Ecommerce Strategy and digital marketing channels optimization - SEO, SEM, email, affiliates - for high-profile accounts.
Technology Solutions
Sales Support
Software Implementation
Requirements Analysis & Specification
Leadership

• Logic Design
• Verilog
• ASIC
• CPU Design
• Computer architecture
• HDL

Personally responsible for designing RISC microprocessor pipeline and execution control and cache subsystems. Project leader for System on Chip project that started from logic design through manufacturing and test.