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RssPerformed ASIC chip design and verification at component level as well as chip level using various HDLs like SystemVerilog and Verilog. Provided automation using Perl, Shell, Make scripting languages. Performed Coverage Driven Verification (CDV) and wrote

Looking forward to work as an ASIC design/verification engineer. In my professional experience of 2.5+ years, I've extensively worked on SystemVerilog and Verilog to perform verification of various standard protocols like SDIO, MMC, USB2.0, PCI, AHB AMBA, UART, I2C, Wishbone. Have developed Perl, Shell, Make scripts to provide automation. Also worked on various verification methodologies like OVM, VMM, AVM. I'd be glad to show my talents in the area I've already worked as well as I am eager to develop my skills in the new area as well.

Electronics Engineer

Sacramento, CA

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