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Sr. ASIC-DFT Design Engineer
Verilog/VHDL, RTL design, logic synthesis/DFT-insert, test-compression, boundary scan, MBIST, SAF/TDF patterns generation, and DFT verification.
Electronics Engineer
About Me
Industry: |
Engineering & Architecture |
|---|---|
Occupation: |
Electronics Engineer |
Education level: |
Master |
Will Relocate: |
Yes |
Location: |
San Jose, CA |
