Occupation:Engineering Manager |
Location:San Jose, CA |
Education Level:Doctorate |
Will Relocate:YES |
Description
Work Experience
| COMPANY | POSITION HELD | DATES WORKED |
|---|---|---|
| Marseille Networks, Inc. | Director Of Asic Design Director Of Digital Design, Sns Logic Design | 2/2011 - 2/2011 |
| Foveon, Inc. | Director Of Asic Design | 9/2007 - 9/2008 |
| Telairity Corporation | Sr. Development Engineer/Technical Manager | 12/2006 - 9/2007 |
| Intel Corporation | Design Manager Manager, Baseband Design Team | 7/2003 - 8/2006 |
| Micron, Inc. | Sr. Design Engineer | 4/1999 - 3/2003 |
| Poseidon Technology Inc. | Member Of Technical Staff | 10/1998 - 4/1999 |
| Instrument Inc. | Sr. Design Engineer | 10/1998 - 10/1998 |
| Specifications | Logic And Circuit Design Of A Dual Cache/Program Memory Controller | 6/1995 - 10/1998 |
Education
| SCHOOL | MAJOR | YEAR | DEGREE |
|---|---|---|---|
| Stanford University | Deep Machine Learning | 2019 | Master Degree |
| University of Texas at Austin | Electrical and Computer Engineering | 1995 | Doctorate Degree |
| University of Houston | Electrical and Computer Engineering | 1990 | Master Degree |
Accomplishments
Keywords
