| COMPANY |
POSITION HELD |
DATES WORKED |
|
|
| Zarlink |
Asic/Hardware Design Engineer (04,2000 10,2006)Project Leader/Hardware Engineer Project Leader/Principal Engineer Of The Dvb S Set Top Box (Pd3210)
|
1/1999 - 1/1999 |
| (Confidential) |
Fpga Engineer (09,2018 01,2019)
|
/ - Present |
| (Confidential) |
Drive Control Engineer (08,2016 06,2018)
|
/ - Present |
| (Confidential) |
Senior System Engineer (02,2016 08,2016)
|
/ - Present |
| (Confidential) |
Senior Fpga Engineer (02,2015 11,2015)
|
/ - Present |
| (Confidential) |
Senior System Engineer (04,2014 10,2014)
|
/ - Present |
| (Confidential) |
Hardware/Fpga Engineer (10,2012 07,2013)
|
/ - Present |
| (Confidential) |
Asic Design Engineer (03,2010 09,2010)
|
/ - Present |
| (Confidential) |
Hardware Design Engineer (02,2007 01,2009)
|
/ - Present |
| (Confidential) |
Hardware/Fpga Engineer (12, 2019 06,2020)
|
/ - Present |
| (Confidential) |
Fpga Engineer (05,2019 09,2019)
|
/ - Present |
Description
