Technology professional with 15 years of experience relating to Neuroscience and more than two decades of experience in computer architecture, memory and storage industry, including system concept development, product development, product management, engineering management, representation of company in Standards organizations (JEDEC), University relations and Intellectual Property Protection. Project management using Agile, MS-Project. Writing of marketing requirement documents (MRD), product requirement documents (PRD) and documentation of architectural design considerations documents (ACD). Generation of request for quote (RFQ) and request for proposal (RFP) responses including cost and schedule forecast. * Major emphasis on non-volatile memory technologies such as NAND flash. Strong interest in emerging technologies including scalability forecast. Co-inventor of additional security through memory address scrambling in addition to data encryption. Member at JESD 219 TG (SSD Endurance Qualification). Go-to person for problem solving and out of the box thinking solutions. * Excellent working knowledge of intellectual property rights, specifically US and International patent systems (America Invents Act, Unified European Patent System). Generated OCZ Technology Group, Inc. and WaytronX patent portfolios from scratch, resulting in ~US$ 6 million valuation (OCZ) and US$ 0.5 million (WaytronX selling price) within 3 years and 9 months, respectively. * Able to jump in and understand and analyze operational, strategic issues, competitive advantage, product positioning, identification of strategic partners and generate intellectual property protection (patents, trademarks). * Strong foundation in engineering, math and physics. More than 50 issued patents on DRAM and flash memory, solid state storage, memory -based encryption systems and cooling, BCI, several additional pending applications on NVMeoF and data-center appliances. * "Developed" and coached several generations of engineers from entry level to independent project owners. * Excellent communication skills, specifically, listening to customers to understand specific needs and translating their wishlist into design requirements while also being able to propose alternative solutions that may be better matches for the specific needs of the customer. * Comfortable working with corporate and patent attorneys on any intellectual property-related issues. Expert knowledge of patent writing (~100 patent applications including for 3rd parties), claim construction, analysis and interpretation/assertion. Prior art search of multilingual data bases including university papers and doctoral theses. Licensing and litigation support, generating detailed claim charts, non-infringement and invalidation defense. Expert Witness on behalf of Intellectual Ventures. Depositions at USPTO and successful defense of challenged patents. Contract work for IP-Ingenuity, VisionaryIP, Intellectual Property Engineering, BHIPLaw. DETAILED TECHNICAL EXPERTISE * Excellent knowledge of memory subsystem performance bottlenecks: - Power consumption vs. performance, latency masking, peer-to-peer transfers and disaggregate memory and storage concepts. * Knowledge of FTL, metadata, physical region pages (PRP) and scatter gather lists (SGL) - Software defined hardware, SD-WAN - eMMC, SAS/SCSI, NVMe - NAND dynamic/adaptive error detection and correction - NAND adaptive programming and error/wear anticipation - White papers and marketing collateral on disaggregated storage - White papers on SSD and HDD functionality and architecture * Drove transition of OCZ Technology Group, Inc from DRAM to NAND flash SSD product portfolio to become third largest SSD vendor globally. * Initiated acquisition of Indilinx to make OCZ the SSD performance leader - Drove transition to Sandforce controller-based solutions - Coordinated between HW and FW teams for feature definition, schedule, product development milestones, and deliverables. * Developed concept and patented for OCZ (among others): * File system-based wear leveling (similar to Open Channel SSD) - Dynamic programming mode change (SLC to MLC/TLC etc.) - Adaptive failure anticipation and automatic back-up after reaching error threshold - Add-on SSD cache for spinning HDDs. - MRAM-based metadata cache for SSDs - Memory address encryption (instead of data encryption) as additional security * Excellent understanding of data center infrastructure and requirements: * Metadata caching, hierarchical storage management and virtualization. - Computer and storage architecture (HDD, SSD) and high performance systems (electronic, electro-mechanical), including virtual tape libraries and back-end storage * HDD and SSD architecture, drive encryption, caching, cloud storage, - AI-ML (deep learning, feature extraction) and big data analytics. * Computer architecture and CPU microarchitecture * x 86 microarchitecture - DSPs: GPUs and AI/ML-targeted FPGA-based Adaptive Computer Acceleration Platform such as Xilinx Alveo /Versal. - Good understanding of bottlenecks and trade-offs such as pipeline depth vs. miss, adaptive floating point precision etc. * Development, debugging and cost reduction: * Newisys "Double Diamond" server: dual Grantley CPUs, split motherboard in clamshell configuration including four IOCs + expanders in SBB2 form factor - Newisys Apex (dual Grantley) server board. Slashed board manufacturing cost by 70% through PCB cost optimization and component changes * Design of AMD ROME based high performance NVMe storage server with maximum utilization of PCIe switch fabric of ROME's IO die. Dual pathing NVMe for High availability solutions, blade server concept development for Viking Enterprise solutions. - Co-developer of NVMeoF Systems at Viking Enterprise Solutions. Conceptualization of disaggregated server and persistent memory appliances including access protection and encryption of software-defined storage / memory systems. Conceptualized complete roadmap for NVMeoE series of appliances in 2U-72 configuration (72 NVMe drives). - Schematics and layout review for high speed routing, power, cost optimization, stack-up definition and component selection * Co- developer of the OCZ neural impulse actuator (nia) * The first commercially available brain-computer interface (BCI). computer system engineering, mechanical engineering, forensics, protocol analysis, biotechnology, microprocessors, memory and thermal management technology. * May 2003 - Present: Founder and Technical Director, DataSecure LLC. - Development of novel, memory-based encryption technologies. - Several Patents on encryption and memory controller optimization. * Nov 2002 - Sept.2003: Seagate: Contract work on Hard Disc Drive technology and Serial ATA. - White Papers on ATA and SCSI interfacing, command structures, command queuing and performance analysis and metrics. - SiliconAquarius, Tenfold Faster, Zettacore: Contract work relating to memory controller interfacing, development of custom memory interface prototypes. * April 2000 - October 2002: Senior Applications Engineer at Ramtron/Enhanced Memory Systems. * May 1988 - September 2000: R&D positions in various academic institutions related to Ophthalmology and Neuroscience / Cell Biology/ Psychology. * January 1979 - July 1979: Engineering Internship with Motoren and Turbinen Union (MTU/Mercedes) Friedrichshaven, Germany, mechanical engineering and failure analysis.
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