* Invention and software realization of state-of-the-art IC design optimization framework based on modern graph theoretic methods, nonlinear optimization and machine learning. It is the only framework in EDA industry that defines a systematic and theoretically justified approach to achieve an optimal IC design implementation in the terms of chip speed, area and power consumption. * Development of novel efficient layer-wise method for deep learning of feedforward neural networks. This method combines the backpropagation principle, layer-wise learning concept and advanced algorithms to solve a set of linear equations. Practical applications of the method demonstrate the top generalization performance in many real-world machine learning tasks. * Designing of state-of-the-art graph algorithms for fast and highly accurate recognition of images of subcircuit patterns in a large-scale IC. These matrix-oriented algorithms integrate modern graph optimization for solving subgraph isomorphism problem and sophisticated soft-decision making techniques. The software tool implementing the above algorithms is used as a part of custom IC design flow by leading semiconductor companies. * Development of cutting-edge graph representation learning techniques based on deep learning algorithms and graph-theoretical methods. These techniques exploit novel 'deep graph matching' concept to construct robust and highly-discriminative graph features. The usage of such features in IC analysis and characterization results in 5x dimensionality reduction with no accuracy degradation. * Invention of break-through techniques for statistical analysis of ICs using information theoretic (IT) principles. These techniques exploit mutual information, entropy and other IT concepts to model complex dependencies of sources of variations in IC graphs. The software implementation of the IT method is exploited by many EDA companies to ensure a high accuracy of statistical IC estimations for arbitrary sources of variability. * Architecturing and software implementation of a new high-performance tool for analytical placement of circuit components on IC chip. The key elements of the invented placement methodology are Hessian-free nonlinear optimization techniques and B-spline curve fitting for a smooth modeling of objective functions. The new analytical placers outperform standard academia and EDA industry placer in both runtime and quality of results. * Designing of advanced digital signal processing (DSP) algorithms (fast convolution, fast Fourier transform, etc., ) based on novel number theoretic transforms over direct sums of finite fields. The new algorithms ensure extremely fast and error-free signal processing using operations in finite algebraic structures. This approach allows construction of multiplier-free parallel and pipeline-based specialized DSP processors.
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