Description
IC Design, Verification, Verilog, System Verilog, Mixed-signal, DC, RC, DFT, Tetramax, Primetime, Formality ET, LEC, Tempus, SPICE/Spectre, AMS, Tcl, Python scripting. 10 U.S. patents.
IC Design, Verification, Verilog, System Verilog, Mixed-signal, DC, RC, DFT, Tetramax, Primetime, Formality ET, LEC, Tempus, SPICE/Spectre, AMS, Tcl, Python scripting. 10 U.S. patents.