Description
Work Experience
| COMPANY | POSITION HELD | DATES WORKED |
|---|---|---|
| (Confidential) | Deputy Director, Technology Enablement Test Chip | 7/2015 - Present |
| Microelectronics | Sr Manager (2nd Line)Manager, Technology Design Rules Development Engineering Manager, Technology Enablement Physical Layout Design Rules Engineer Kerf (Dice Lane) Design Engineer Laboratory Technician | 2/2008 - 6/2015 |
Education
| SCHOOL | MAJOR | YEAR | DEGREE |
|---|---|---|---|
| Polytechnic University | Electrical Engineering | 1989 | Bachelor Degree |
Accomplishments
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