PROFESSIONAL SUMMARY Versatile, passionate, results driven professional who has successfully led wide range of analog and mixed signal circuit designs. Led design of on chip voltage regulator for Oracle's next generation SPARC processor from feasibility to tape out in TSMC Fin-Fet 10nm technology. Extensive experience in various stages of high speed IO design and DDR PHY design starting from customer requirements to post silicon bring up and support. Outstanding oral and written communication, and strong analytical skills. Earned recognition from management for producing unequaled results individually and as a team member.

Highlights:

• Distribution
• Hardware/Systems
• IEEE
• MUX
• Noise
• Phase Lock Loop (PLL)
• PLL
• Rms (Dec Data Mgmt Sys)
• SAP BW module
• Spread Spectrum Technology (SST)