SUMMARY Analytical Design and Verification Engineering professional with experience in architecting multi-layered re-usable Self-Checking Testbench Environments. Effectively creates Verification plans, develops Verification Environments using Bus Functional Models, Transactors, Monitors, Assertions and Checkers, Design Debugging and Issue Tracking for Unit and Block Level Verification as well as ASIC Verification to reach Coverage Goals. Proven success in enhancing existing systems with new features and performance improvements. Core strengths in: * Verification Partitioning and Development Flow * Directed and Coverage Driven Random Verification Flow * I/O Protocols and Controllers Verification

Highlights:

Companies I like:

apples

• VERILOG
• Altera
• Asic
• ASIC Verification
• C/C++ Programming Languages
• Compiler
• Debugging
• Design Specification
• Electrical Engineering
• Engineering