Professional engineer position in Electronic Design Automation, CAD methodology development, ASIC/SOC design verification role TECHNICAL PROFILE * Lead design engineer in product validation developed testplans, created/automated tests in Verilog/VHDL, ran regression tests for Cadence Hardware Acceleration/Emulation tools * Experience in Analog/Mixed signal design and worked with IEEE VHDL-A working group In the development of Analog Language extension to VHDL * Expert in SPICE modeling, developed AnaVHDL, a spice-like simulator written in VHDL includes basic device models from SPICE2G6 (Berkeley Version) and reads SPICE input-deck * Experience in benchmarking for RTL simulation performance optimization * Experience in benchmarking for Magma physical synthesis tools (50K+ gates) * Developed training course for hardware acceleration system at Sun Microsystemsc * Managed projects (1.5 million) for Rome Airforce Contracts * Customer support experience for EDA tools * Developed many RTL VHDL models (15,000+ lines) * Involved in Project Proposals in Airforce contracts * Trained UVM at Cadence COMPUTER SKILL * Verilog, SystemVerilog, VHDL, UVM, CPF, C, C++, Java, SQL, Perl, XML, HTML, bash/cshell * Cadence Palladium System, Incisive, Synopsys Design Compiler/prime Time, Cadence Verilog-XL/NC, Synopsys VCS, Magma Physical Compiler * UNIX, Windows, Redhat Linux, Mac OS X, DOS

Highlights:

Companies I like:

Intel, AMD, Apple

• VERILOG
• Intel
• Test
• Test Plans
• VHDL
• Cadence
• Infrastructure
• Local Area Network
• Networking
• Project Management