SUMMARY Senior physical design engineer with 18 years' experience in various layout styles including custom, cell-based and RLS, with particular expertise in memory compiler design. Extensive experience with 14nm and 10nm processes technologies. Skillful in layout planning, implement, verification and debugging. Experience in: * Layout design CAD tools: GeneSys, Opus, Virtuoso, Hercules, ISS, RV, SURF * Physical verification checks: LVS, ERC, SOFT, DRC, DFM, Density, ANTENNA, ESD * layout reliability analysis: EMIR, signal EM and power grid integrity

Highlights:

• Compiler
• Intel
• Intel Microprocessors
• Layout
• Layout Design
• Macro (Predefined Code)
• Mask
• Microprocessors
• Noise
• Phase Lock Loop (PLL)
• analog