Occupation:Engineering Manager |
Location:San Jose, CA |
Education Level:Doctorate |
Will Relocate:YES |
Description
SUMMARY OF QUALIFICATION I acquired extensive executive leadership and hands-on technical R&D expertise in IOT, SoC, ASIC, IP, NVM NOR, OTP, high speed serial IO, SerDes, and Analog Mixed Signal products. Large and cross sites RD teams leadership and project management experiences. I have diversified industry experience with 2 years working in the FAB as process integration engineer and 2 years as a product engineer in flash memory and over 20 years of Analog/Mixed Signal/NVM/DDR in product and SoC IP design and management experience. Held 8 US patents with Intel and 6 patents with GUC and 4 patents pending with XMC and published more than a dozen papers in the field of circuit design and solid state device physics. Pioneered and founded high performing SerDes/memory/data converter IP team in SoC design service company GUC (TSMC Design Service and IP subsidiary). Key IP portfolio in production including 10G+/28G SerDes KR/XFI/EPON/GON, PCI-e Gen3, SATA 3.0/SAS 2.0, USB 3.0/3.1, DDR4/3/2/LPDDR3/2, OTP, NVM (SPI NOR), and LC tank ultra low jitter PLL. Initiated 28G SerDes R&D for 100G Ethernet application, and an Uni-PHY covering multiple standards up including SAS 3.0 (12Gbps) and PCI Gen4 (16Gbps). IOT experiences on extremely low power NVM Memory IP and products developed in Pericom Corporation and Kilopass Technology, Inc. Recent achievements including industry's leading wide voltage range (3.8V-1.4V) SPI NOR flash. Worked on and familiar with advanced technology nodes such as 28nm HKMG processes (28HPC/HPM/HPC+/LP/HPL), 16nm FinFet (16FF+, 16FFC), and 10nm/7nm FinFet while working with TSMC/UMC/SMIC/GF, etc. in prior jobs in GUC and Kilopass.
Education
| SCHOOL | MAJOR | YEAR | DEGREE |
|---|---|---|---|
| University of California | Electrical Engineering | 1993 | Doctorate Degree |
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