Professional Summary: * Mask Layout Designer with over 30 years of experience in Full custom IC Layout. * Created layout for high speed Receiver and Driver Chip including IO pads and their ESD circuitry, RF, Analog and Mixed Signal blocks, Mixers, Bandgaps, Amps, ADC's and DAC's Switch Caps. Building layout with Clones and Group configuration. * Cadence - Virtuoso, Virtuoso XL, Knowledgeable in device matching, pitch matching, balancing, and shielding of critical devices, differential signal routing. Able to independently perform efficient debugging of Calibre verification results using RVE with ability to implement timely layout corrections of results. * Experience with Floor Planning of Blocks, Standard Cell creation of CMOS, BiCMOS and PCELL devices and Finfet design process. * UMC 90nm, 65nm, 45nm, 40nm, 22nm, 18 and 16nm Finfet CMOS processes. * I easily integrate into existing project teams and work with other contractors or direct employees. * Self-motivated, attention to detail, good communicator with team.

Highlights:

• CMOS
• Phase Lock Loop (PLL)
• PLL
• Layout
• Mask
• Cadence
• Advanced Mobile Phone Service (AMPS)
• Attention to Detail
• Configure
• Debugging