Lucent Technologies Work Values

Daily Duties at Lucent Technologies:

Served SONET ASICs optical networking department to design and verify multi-million gate telecom ASICs used in Metro Digital Multiplex (DMX), Wave Star and DDM-2000 products. The SONET ASICs were designed in 0.3um -0.16 um CMOS technologies to run in the 155MHz region with LVDS I/O speeds up to 625MHz to support OC1 - OC192 cross-connect, VT (Virtual Tributary) grooming and Data Communication Channel (DCC) support. Develop soft IP library of reusable cores to be used in future ASICs. Develop VHDL/Verilog SONET network processor test bench using telecom work bench components. Wrote test plans and functional tests ran extensive unit level and chip level RTL simulations using ModelSim and IKOS. Wrote Verilog/VHDL code for major blocks in SONET processors: VT cross-connect processor, pointer processor, HUB, SONET framer, multiplexer, de-multiplexer., microprocessor control interface, 16/4 port DCC controller. Subject matter expert (SME) on DFT design issues. Wrote DFT, BIST, MEMBIST guidelines manual for designers and verifier to follow on all ASICs. Provide training on do’s and don’ts in DFT design and verifications of SONET ASICs Designed and implemented internal scan and generated ATPG vector to achieve > 95% stuck @ fault coverage. Designed and implement boundary Scan (JTAG, IEEE 1149) in all SONET ASICs and generated JTAG vector. Develop functional and scan vectors to run on HP 35000 ATE tester for SONET/SDH ASICs and provide foundry technical support on IC packaging. Wrote Perl scripts to automate setup and running of gate level functional, timing and scan vectors on the IKOS hardware accelerator. Performed system test and validation of multi layer PCB with SMT ASIC capable of high-speed digital data rates: OC-192, OC-48, and OC-12. Wrote DC shell scripts to synthesis major design blocks. Performed static timing analysis, clock tree buffering, and signal integrity analysis. Extracted STAMP/ ILM models for faster timing closure using Avanti (Apollo, Jupiter) and Synopsys PC flow Debugged and lab tested high-speed digital PCB design with in-house ASICs and Xilinx Vertex FPGAs. .

What they like about Lucent Technologies:

Working in an organization that is technologically advanced, creative, and innovative is critical in your assessment of hiring companies. Less important to you are stability of the organization, the length of time an organization has been in business, and the business' plans for the future. You prefer a fast-moving company that will take risks to achieve its goals and objectives. The length of time the company has been in business is irrelevant. Maintaining status quo is unnecessary. You thrive on change, uncertainty and the upside of potential business risks, especially those associated with innovation. Stability for the long haul is not nearly as important as is working in an atmosphere that is charged with a sense of urgency and constant change.

Tags

C, CPLUSPLUS, ASIC, FPGA, DSP, VERILOG, VHDL, SYSTEMVERILOG, UVM, OVM, VMM, UNIX, LINUX, XILINX, ALTERA, ATMEL, MATLAb, SIMULINK, ETHERCAT, ETHERNET, RS232, RS485, COLDFIRE, SONET, VectorCAST, RTOS, PERL, TCL, ShELL, PYTHON, DFT, CodeWarrior, Code Composer, XML, PCB, JTAG, UART, I2C, LVDS, HDSL, SPI, DDR, JIRA, Perforce, UBUNTU, LABView, HTML

Skills

VHDL, Verilog, C, C++, DFT, Python, MATLAB, SIMULINK, Verification, SystemVerilog, EtherCAT, RTOS, DSP, ASIC, FPGA, Code Warrior , Code Composer

These are some of the questions we asked our climbers about their experiences with Lucent Technologies: