Fujitsu Microelectronics America Work Values

Daily Duties at Fujitsu Microelectronics America:

*****Design for Test: Interconnect Chip for Supercomputer CPU (65nm/45M Gates) • Wrote Verilog RTL for serial test interface to control SerDes testing. • Implemented On-Chip Clock Generator for at-speed test with on-chip PLL. • Developed the methodology for at-speed testing using Cadence Encounter Test. • Ran Equivalence Checking to compare Pre/Post DFT insertion netlist. • 1149.6 (AC JTAG): Wrote Tcl script to hook the SerDes RX/TX Pads along with other Chip I/Os in Boundary chain. Created combined BSDL for 1149.6 and 1149.1 • Verification of 1149.6 feature using verilog pattern, to control the TAP FSM and AC test signal. • Pattern generation for Scan/On-chip Compression, JTAG, MBIST, IDDQ and Parametric tests with Cadence Encounter Test. Vector generation based on STA results. • Gate level simulation using SDF for generated verilog patterns. • Debugged post silicon ATE failures using Encounter Test Diagnostics and custom patterns. ***** Design for Test: Audio/Visual Codec Chip (65nm/8M Gates) • DFT Insertion done using Mentor Graphics DFTAdvisor. • Created Synopsis Delay Constraints for different test modes. Timing closure for different corners using PrimeTime • Generated ATPG patterns Mentor Graphics Fastscan and TestKompress. • MBIST pattern generation and verification using internal tool. • Ran Static Timing Analysis using PrimeTime. Vectors generated based on STA Results. • Performed gate level simulation using SDF annotation for generated verilog patterns.

What they like about Fujitsu Microelectronics America:

Organizations with strong, centralized leadership are particularly attractive to you. You require a work environment with leadership that aggressively seeks to expand and grow the business and does so in a visible and decisive manner. In general you prefer to work in an environment in which there is a strong link between leadership, its actions, and a strong set of company-wide values.

Tags

DFT, Verification, Mentor, Verilog, C, Static Timing

Skills

Design for Test, Verification, Verilog, Cadence, Mentor Graphics, PrimeTime, PERL, C/C++, Fastscan, TCL, Ncverilog, Debussy, Verplex, Specman, Clearcase/CVS/Subversion, VCS

These are some of the questions we asked our climbers about their experiences with Fujitsu Microelectronics America: