Custom One Design Inc. Work Values

Daily Duties at Custom One Design Inc.:

Single chip CMOS Direct Conversion Tranceiver (1.4 GHz RF-components), single chip low-IF CMOS GPS-receiver (3.5 GHz RF-components). Sigma-Delta Frequency Synthesizer, PLL, Subharmonic Mixer, Phase shifter, CML-Prescaler, DSP. Design the different types of the Sigma-Delta - incremental Sigma-Delta ADC (10 times faster thermal noise suppression than standard architecture, few times faster quantization noise suppression), Band-Pass Sigma-Delta ADC, digital Sigma-Delta modulator for Frequency Synthesizer. SC-circuits design. Software Defined Radio (SDR) - subsampling BP-Sigma-Delta receiver, totally digital control currier frequency and bandwidth. Multi-phase oscilator and phase grid generator for UWB-radars – 256 phases, step 20ps, jitter<3.5ps Layout design: 1. I/O cells layout - I/O cell library, ESD, RF-ESD, Pad Ring design. Layout provide uniform current distribution to avoid overload ESD-protection. 2. Digital layout – Standard Cell Library, Place and Route, RAM/ROM layout. High frequency CML cells for RF applications - frequency division 5 times faster than CMOS. 3. RF/Analog layout Automatic generation of the component’s layout (Mentor IC station, Tanner EDA) - RF /Analog transistors (including guard rings) - MIM-Cap - Inductance and manual routing of the RF/analog components. This approach allows to get good correspondence between component’s layout and spice models, results are relatively independent on layout person. Special technic to improve device matching for analog components (centroid). Special high symmetrical RF-layout for harmonics and noise suppression. Symmetrical baseband layout to minimize I/Q-distortions. High frequency layout, minimization of parasitics, shielded buses, I/O cells with low EMI radiation. Component isolation (digital, analog, RF). Triple well isolation. Substrate noise reduction. Low noise digital library and I/O cells. High voltage layout (LDMOS, component isolation, latch-up prevention), radiation hardened layout. Top level floor-plan and routing, power/GND buses distributions, clock buses distribution. Project verification (DRC/LVS, parasitic extraction).

What they like about Custom One Design Inc.:

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Tags

Mixed signal ASIC, IC layout design, Sigma-Delta ADC, Verilog, Tanner, Mentor, Matlab, Simulink

Skills

Schematic design/simulation/layout RF, Analog and Digital components, project verification (DRC/LVS, parasitic extraction)., Synthesis(Verilog/VHDL), digital cells routing, IO-cells design, FPGA design., Experienced with PC and SUN station: “Mentor Graphics” (“Calibre”, “HDL Designer”, “Leonardo”), “CADENCE”(Schemaic/Layout), “Hspice”, “Tanner EDA”, Matlab/Simulink, C, Tcl.

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