Intel Corporation Work Values

Daily Duties at Intel Corporation:

System Level Emulation Engineer (Sept 2005 – August 2008) 1. Transactor Based Emulation (EVE Zebu emulator): Released the 1st SystemVerilog based transactor driven Falcon emulation platform for 32-bit Intel x-86 based Atom CPU (Silverthorne) enabling faster pre-silicon verification increasing coverage and reducing TTM. Responsible for helping develop the Falcon tool (EVE Zebu emulator + Intel front end), Raven tool working on the front end development involving the Syntax checker (Esperanto), Compile flow (creating objects, flattening hierarchy) and Synthesis (timing analysis, net generation). Responsible for providing weekly model builds after running and debugging pre-silicon tests on RTL model. Responsible to recode RTL to replace the non-synthesizable constructs or add code for validation teams. Responsible for test debug where all test failures on emulation were re-run on VCS and debugged. Responsible for EVE-Zebu hardware, fpga board upgrade and debug, primary interface with the AE from EVE, emulator install, host server issues, netbatch issues working with several other teams at Intel. Tbx emulation provided speeds upto 60 khz as compared to 20hz for VCS based functional verification. 2. Hardware In-Circuit Emulation (Mentor Veloce/Vpro emulator): Lead the implementation of the complex ICE platform using Celeron (NWD) CPU board, IO board and memory fpga board as the memory speed bridge to the DDR2 for Intel Atom based SOC called Lincroft. Executed the north cluster reset, NWD CPU out of Reset, Clock Synchronization, FSB access, Register reads, memory read-write, accessing device registers for Lincroft using an external reset signal provided by the altera fpga on the IO board. Implemented the Split Speed System for faster execution using the RAMBO board as speed bridge. Integrated Lincroft with the Langwell Chipset to bring up the true Intel Atom based SOC with USB and PCI. Facilitated failure debug of design bugs by using visibility and debug features such as memory dump, Modelsim/Synopsys waveform debug, memdump compare, Velocegui/Falcon debug. Enabled Post Silicon Val in Pre-silicon time-frame, thereby, reducing TTM, increasing SV coverage, enabling OS and firmware development with speeds in the range of whooping 600 khz – 1 Mhz core clock!! Responsible for Mentor Veloce Hardware, hardware boards (IO board, CPU board, RAMBO memory board), s/w installation, server farm, emulator host system, board issues, board upgrades, firmware upgrades etc. Hardware Electrical (Analog) Validation Engineer (August 2008 – May 2009) Responsible for developing EV test plans, studying specs, setting up SV/DV platforms, execution. Debugged hardware board issues, silicon bringup issues, calibrated LA’s and O’scopes Accomplished planned Silicon Power-On, System Marginality Validation (SMV), Signal Integrity Validation (SIV), and Bench Design Verification (BDV) with 100% coverage and validating against the industry specs. Increased test coverage by 30% by automating the data collection process for SIV using phython scripts Represented the AnV Validation team in higher coordination forums, validation forums and design meetings successfully communicating risks, schedule and showstopper issues.

What they like about Intel Corporation:

Organizations with strong, centralized leadership are particularly attractive to you. You require a work environment with leadership that aggressively seeks to expand and grow the business and does so in a visible and decisive manner. In general you prefer to work in an environment in which there is a strong link between leadership, its actions, and a strong set of company-wide values.

Tags

Perl Scripting, Verilog, SystemVerilog, VHDL, SIV, SMV and BDV, Tbx emulation, In Circuit Emulation, VCS, Debussy, functional debug, xilinx virtex 5, system validation, analog validation, silicon power-on and debug, ITP scripting, C/C, Functional Verification, Assertion based verification, Debussy waveform functional debug, ITP scripting and debug, Intel, Mobility Group

Skills

FPGA Prototyping/Emulation, ASIC Functional Debug , Commercial Emulators (Veloce, Falcon, EVE), Analog Validation using SIV, SMV, BDV, System level Board Debug, Intel x-86 Architecture, Perl Scripting, C/C and OOP, PC buses (FSB, Memory Bus, PCIe, CDMI), Thermal Validation, Silicon Power On and debug, SOC reset sequence, clocking, link training, addressing, architecture, Intel ATOM low power design, Lab equipment (LA, Oscope, DMM), Simulation Acceleration using Emulation, SOC validation using In Circuit Emulation, Project planning and management, Microsoft Office, Functional Verification using simulation, Assertion based verification, Hardware board design, schematic, Hardware board debug, LA debug, Timing analysis for FPGA boards, Clocking for SOC designs

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