Sun Microsystems Work Values

Daily Duties at Sun Microsystems:

MMU Tag (SRAM) Ultra Sparc VII Feb 2005 – Jan 2006 Designed and implemented approximately 1KByte, 2-Way Set Associative Tag SRAM @ 2.3GHz using 65nm technology. Each way has four banks and each bank split into two array with 8 Entries and 72 Bits/Entry. The cell has 1r1w port thus supports simultaneous read and write operation to the Arrays. The block supports eight invalidation writes apart from normal read and write to the array. Tag does 34 bit wide comparison along with 35 bit parity check. Created Critical Path Schematic and ran simulation at various process corners and made sure that all design margins are healthy. Completed Backend Verification: Innologic Symbolic Simulator for RTL vs. Schematic Equivalence, Memory Test Plan (DFT), Noise Tool, Clock Grid Check, IR/EM, Timing Using Array Black box Models in STA and Power Estimate. IWRF (CAM + RAM) Ultra Sparc VII April 2004 – Jan 2005 Design and implemented Integer Working Register File (IWRF) @2.4GHz using 65nm technology. CAM features 32 entries and is 9 bits wide, ,the CAM cell is designed with 3 Write Ports and 10 match port, RAM features 32 entries and is 64 bits wide ,the RAM cell has 4 Write Ports and 7 Read Ports. Source data for IEU and DCU units are Read from IWRF in a 2-cycle operation i.e. source register address lookup (compare) done in CAM and Data is read from matching entry in the RAM, similarly the results from IEU and DCU units are written into IWRF in a 2-cycle operation i.e. destination register address written into the CAM and corresponding data written into the same entry in RAM Created critical path schematic and margin documentation, ran simulations with various process conditions and made sure that all design margins are healthy. Completed backend verification for Noise, clock grid, EM/IR and Timing FIFO (Register File) Ultra Sparc VII Jan 2004 - June 2004 Designed and Implemented 32 Entries, 64 Bits/Entry register file with 2-write 1-read port @ 2.3GHz using 65nm technology. Designed 2-write, 1-read cell and performed Statistical Simulation based on Gaussian variations for process offsets. Did extensive simulations to come up with the transistor sizing for the cell based on writability, leakage and trip point. Generated design specs (floor plan, functional diagrams, timing waveforms). Created Critical Path Schematic and ran simulation at various process corners and made sure that all design margins are healthy. Did all backend verification: Memory Test Plan (DFT), Noise Tool, Clock Grid Check, IR/EM, Timing Using Array Black box Models in STA and Power Estimate. CAM Cell Analysis June 2003 - Dec 2003 Did design analysis between pass-gate style and Static XOR type CAM cell. The analysis looked at the affect of leakage on the match-line based on array width, the affect of noise sensitiveness inside the cell and speed i.e. the discharge of the match line and size of the cell. Integer Register File Cell for Ultra Sparc VII Dec 2002 - May 2003 Design 4-write 7-read register file cell with two active cell within a register cell, the cell is designed to support instructions from two strands simultaneously, patent filed. Did extensive simulations to come up with the transistor sizing for the cell based on writeability, leakage and trip point using Gaussian variations for process offsets. Integer Register File Ultra Sparc III & IV: Oct 1999 -- Dec 2002 Characterized Integer register File for Ultra Sparc III & IV (s & i) series at 1.25 GHz with 0.13micron technology. The design is logically composed of two distinct register files, Working Register File (WRF) and Architecture Register file (ARF). The WRF is a 32 64-bit register. The WRF has 3 write Ports and 7 read ports as well as single 1984-bit wide transfer write port. The ARF has 160 64-bit registers organized into 8 register windows and 4 sets of global registers. It has three write Ports and a single 1984-bit wide transfer read port to the WRF. D$ Parity RAM: Oct 1999 -- Dec 2001 Characterized D$ parity RAM for Ultra Sparc III & IV (s & i) series at 1.25 GHz with 0.13micron technology. The 2KByte Memory Array stores a single bit parity for every 32-bit word of the D$ Array or each entry line stores a pair bit for each of the four double word. D$ parity RAM is composed of two sub-arrays i.e. even and odd array each is 128 rows x 16 columns x 4 banks memory array. Comparator Design: Nov 1997 _ September 1999 Characterize 28bit I$ tag comparator for Ultra Sparc II with 0.18 micron technology @ 450MHz Timing Work: Nov 1997 _ September 1999 Involved in analyzing and solving maxtime and mintime path for Ultra Sparc II processor @ 450MHz

What they like about Sun Microsystems:

Working for a company with an emphasis on social values and helping society is a clear and important priority for you - a critical factor in who you choose to work for. In contrast to other factors, you place an organization's reputation for fairness and concern for the community above most other aspects of the company. As you search for a new job opportunity, it is usually possible to find out if the company is involved in the community and/or if it is addressing problems and issues in society. Pay special attention to non-profit organizations and those specifically involved in social action. Moreover, speaking with current and former employees should enlighten you to perceptions of the fairness of the company's leaders and the treatment of employees.

Tags

SRAM Designer, Bay Area SRAM Designer, Circuit Designer, Memory Designer, Digital Designer, CAM Designer, Register File Designer, Application Engineer, Sales Engineer, Electrical Engineer, SRAM Designer in Austin, SRAM Designer in Phoenix, SRAM Designer in Boston Area, CAD Engineer

Skills

Software Programming: Java(Expert) C(Proficient) , P&L responsibilities, Presentation, Technology Solutions, Skilled Memory Designer, Circuit Designer, Digital Designer

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