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Online Resumes with "Chip Designing"
chip design expert
Ideal Companies: intel pasemi
Tags for this Online Resume: cmos, bicmos, cadence, vlsi, drc, lvs, calibre, sige
IC designer -entry level
To work for a reputed company in the area of chip designing and its logical implementation and contribute my best to it .
ASIC/SoC design engineer
To excel in the field of ASIC/SoC engineering and work in a challenging work environment and contribute positively to the growth of the technology industry.
Tags for this Online Resume: ASIC design engineer, synopsys VCS, verilog HDL, System Verilog , SVA, C++, CADENCE , schematic entry, layout, PLL, USB, AMBA, system on chip design
Performed ASIC chip design and verification at component level as well as chip level using various HDLs like SystemVerilog and Verilog. Provided automation using Perl, Shell, Make scripting languages. Performed Coverage Driven Verification (CDV) and wrote
Looking forward to work as an ASIC design/verification engineer. In my professional experience of 2.5+ years, I've extensively worked on SystemVerilog and Verilog to perform verification of various standard protocols like SDIO, MMC, USB2.0, PCI, AHB AMBA, UART, I2C, Wishbone. Have developed Perl, Shell, Make scripts to provide automation. Also worked on various verification methodologies like OVM, VMM, AVM. I'd be glad to s...
Ideal Companies: Intel, AMD, Broadcom, NVidia, Qualcomm, Synopsys, Cadence, Freescale (basically any Semiconductor industry)
Tags for this Online Resume: ASIC design, ASIC Verification, SystemVerilog, Verilog, Perl, Shell, Makefile, Synthesis, Primetime, Design Compiler, USB2.0, AHB AMBA, PCI, SDIO, SPI, UART, C
Electrical Engineer, Long Beach
To work on any state of art job/ project requiring me to instill a greater capacity for my dedicated work. I want to pursue my field of study intensely so as to enhance my knowledge, and work towards the overall advancement of my career and my organization.
Tags for this Online Resume: CAD, Chip Designing, Wireless Communication, Communication Security, Engineering Management, Opnet Modeler, RF
RESUME
Satish Chakkirala 1746 Ximeno Avenue, Apt # 5 Long Beach, CA - 90815 (714)-7944564 satish.0722@gmail.com OBJECTIVE An internship/full time position in the field of Electronics Engineering. Quest to work in a real professional environment, where I can enhance my skills and widen spectrum of knowledge. Also to make an indelible mark in the organization that i serve. Education •California State University Long beach...
2.11+ years of experiance in RTL design using VHDL/Verilog HDL.
Seeking a position as Hardware Design Engineer to work with a focused design engineering team. Career Interests: 1. Reconfigurable Hardware Architectures (FPGA and SoCs). 2. System-On-Chip Design and High Performance Computing Systems. 3. High Performance Memory Controller Architectures. 4. High Speed Serial IO and Communication Protocols.
Associate RF Engineer
To obtain an entry level position in field of Electrical Engineering (VLSI Chip Design) and Telecommunication in order to gain hands-on experience utilizing my academic background and advancing my interest in Wireless services.
Tags for this Online Resume: 3G/UMTS/CDMA, WCDMA, HSDPA/EVxDO, TEMS , Module Tunning, RF
Staff ASIC Design Engineer, San Jose, CA
Tags for this Online Resume: ASIC Design, RTL, Verilog, Chip Design, SDC CDC, Synthesis Formality
Senior Level ASIC and FPGA chip design verification engineer - 20+ years experience OVM/UVM
I am seeking the ASIC or FPGA Design Verification Engineer position. I can offer extensive experience in Verilog, System Verilog or VHDL verification and design, OVM/UVM verification environments, synthesis, timing, and ATPG from start of concept to their release to physical design. I have built up OVM and SystemVerilog test environments from scratch. I have bus Interface skills in design, verification, and debug: SAS and ...
Tags for this Online Resume: Design, Verification, ASIC, OVM/UVM, SystemVerilog, FPGA, SAS/SATA
Semiconductor IC Design Manager, PMP
I am an experienced IC designer in both CMOS and Bipolar device level circuit design. I have experience as a Design manager, Project Manager, and Design Lead. I have participated in every level of chip design from concept and process selection, through design, to final test and product engineering.
Tags for this Online Resume: project manager, design manager, ic design, ic design, SERDES, SERDES, device level design, device level design, cmos, cmos, bipolar, bipolar, Certified PMP
