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Raushan K

ASIC/SoC/FPGA Digital Design and Verification Engineer - 2 Years of Experience in ASIC Design and 1 Year experience in Verification Domain- Near 95825

Occupation:

Electronics Engineer

Location:

Sacramento, CA

Education Level:

Master

Will Relocate:

YES

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Seeking Full-Time/Internship in ASIC/SoC Design Verification/Validation/FPGA. Two years hands on Experience in RTL design and 1 year experience in Verification, including RTL Design, Verilog HDL/ System Verilog, UVM, Code Coverage, Static Timing Analysis (STA), Functional Coverage, Assertions.

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COMPANY POSITION HELD DATES WORKED

LucidVLSI ASIC/FPGA Design Engineer Intern 3/2019 - 8/2019
Verifast Yechnologies ASIC Verification Engineer 9/2018 - 8/2019
LucidVLSI ASIC/FPGA Design Engineer 1/2014 - 4/2016
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SCHOOL MAJOR YEAR DEGREE

California State University Sacramento Electrical and Electronics Engineering 2018 Master Degree
SHUATS Electronics and Communication Engineering, SHUATS 2014 Bachelor Degree
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My work was related in designing the DUT and writing the test fixture, writing multiple test cases to check and verify the functionality of the design and debugging the scripts. Experience in Implementing test bench, self-checking, direct testbench in Verilog and also worked independently to debug the RTL and find the bugs by creating multiple test cases. Writing direct testbench, self-checking testbench, constrained random testbench in Verilog/ System Verilog, designing in RTL. Generated multiple test cases and launched Regression, compared multiple test cases and if it passes then rerun the script to analyze the results
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